MFC2000 datasheet(214/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

9-2

Conexant

100723A

9.1.1

Horizontal Conversion

Conversion in the horizontal direction is performed in this logic block by adding or removing a programmable

number of pixels at the position which decided by the bi-level resolution conversion algorithm. Pixels are added

based on a programmable 7-bit Base-3 counter and the expansion mode bits (2 bits). Input pixel number needs to

be a multiple of 16. The output pixel number of this block is also a multiple of 16.

Table 9-1. Untitled Table

The expected expansion ratio

the expansion mode

the programmed expansion ratio

the expansion result

100%

≤ X < 200%

≈ X

200%

≤ X < 300%

X - 100%

≈ X

300%

≤ X < 400%

X - 200%

≈ X

Pixels are removed based on the same programmable 7-bit Base-3 counter used for the expansion. Data can be

reduced down to 0.0457% (1/2187 x) and expanded up to 399.95% (~4x). To preserve image quality, it is

recommended that an input line be reduced by no more than 2/3 times (66.67%) it's original resolution (this will

ensure that 2 consecutive input pixels will never be removed).

The following block diagram depicts the BRC block diagram. The functions are broken up into the blocks that

represent the imdividule VHDL that make up the BRC design. Note that the two blocks, Vertical ORING and BRC

Out FIFO, outputs are tied together. This represents the fact that only one of these output modes are operational

at time.

BRC In

FIFO

Parallel

Serial

Mux

BRC

Counters

Filter,

ORing

ORING

Algo.

Shingle

Horizontal

Shifter

Serial To

Parallel

Vertical

ORING

BRC Out

FIFO

Resolution Converter

DMA Data

DMA Data Out

DMA Req 8

DMA Req

T4 Serial

Data In

Figure 9-1: Bi-level Resolution Conversion Block Diagram

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