MFC2000 datasheet(209/426 Pages) ETC

209 / 426 page

Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

8-5

8.2

TADC

8.2.1

Function Description

Thermal ADC provides the analog to digital functionality for low speed analog signals. A simplified block diagram

of TADC is shown below.

6-bit DAC

+/- 1/2 bit

9-bit up/down

Counter

6 MSBs

AD[5:0]

senin[0],[1],[2],

or TADCREF

[tadc-simple.vsd]

Table 8-7. TADC Block Diagram

The TADC includes a 6-bit DAC, a comparator and a 9-bit self tracking up/down counter. The up/down counter is

incremented or decremented based on the polarity of the comparator output. The most significant 6 bits of the

counter are used to generate the DAC reference signal to the comparator. The comparator compares this

reference voltage to the external analog input signals, SENIN[2:0], or TADCREF. After settling, the counter value

(and thus the DAC digital value) represents the A-to-D conversion of the input signal. The least significant bits of

the counter are used to average out the comparator fluctuations which occurs at the settling point. The counter is

set to a mid-point value on the power-on reset so that it settles more quickly. The frequency of updating the

counter is programmable.

The TADC can be operated in two modes. By default, the manual mode will be selected. In this mode, the

firmware will select the analog input. Then, the firmware must wait for at least for 256 * tadcclk period to allow the

TADC to settle prior to reading the data. In the automatic mode, the hardware will do the selection for each analog

input in rotation. Each analog input will be selected periodically, and the data from each channel will be stored in

different register at the same rate as channel selection.

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