AD9736BBC datasheet(26/42 Pages) AD

26 / 42 page

AD9736/AD9735/AD9734

Preliminary Technical Data

Rev. PrJ | Page 26 of 42

OPERATION IN SURVEILLANCE AND AUTO MODES

Once FIFOSTAT<2:0> has been manually placed in an optimal

state the AD9736 SYNC logic can be run in Surveillance or Auto

mode. To start, turn on Surveillance mode by setting SSURV = 1

(REG08, bit 7) then enable the sync interrupt (REG01, bit 2). If

STRH<0> = 0 (REG08, bit 0) an interrupt will occur if

FIFOSTAT<2:0> = 0 or 7. If STRH<0> = 1 (REG08, bit 0) an

interrupt will occur if FIFOSTAT<2:0> = 0, 1, 6 or 7. The interrupt

can be read at REG01, bit 6 at the AD9736 IRQ pin.

To enter Auto mode, complete the preceding steps then set SAUTO

= 1 (REG09, bit 6). Next set the SYNC interrupt = 0 (REG01, bit 2),

to allow the phase offset (PHOF<1:0>) to be automatically updated

if FIFOSTAT<2:0> violates the threshold value.

The FIFOSTAT signal is filtered to improve noise immunity and

reduce unnecessary phase offset updates. The filter operates with

the following algorithm:

FIFOSTAT = FIFOSTAT + Delta FIFOSTAT / 2 ^ SFLT<3:0>

Where 0 <= SFLT<3:0> <= 12. Values greater than 12 are set to 12.

SAMPLE_HOLD

SAMPLE_SETUP

SAMPLE_DELAY

EXTERNAL_DELAY

INTERNAL_DELAY

DACCLK

DATACLK_OUT

DATACLK_IN

DATA_IN

CSS1

CSS2

WRITE_PTR1

READ_PTR1

FIFOSTAT

DAC_DATA

Figure 29. SYNC Logic Timing Diagram

Safe Zone

Error Zone

Data ‘A’ can be

safely read from

the FIFO in the

Safe Zone. In

the Error Zone,

the pointers

may briefly

overlap due to

clock jitter or

FIFOSTAT is set

equal to the

write pointer

each time the

read pointer

changes from 7

to 0.

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