Preliminary Technical Data

AD9736/AD9735/AD9734

Rev. PrJ | Page 15 of 42

SPI REGISTER DESCRIPTIONS

REG 00 -> MODE

Reading REG 00 returns previously written values for all defined register bits unless otherwise noted. Reset value in bold text.

ADR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00

MODE

SDIO_DIR

LSB/MSB

RESET

LONG_INS

2X MODE

FIFO MODE

DATAFRMT

PD

SDIO_DIR

: WRITE ->

0, Input only per SPI standard

1, Bidirectional per SPI standard

LSBFIRST

: WRITE ->

0, MSB first per SPI standard

1, LSB first per SPI standard

NOTE: Only change LSB/MSB order in single byte instructions to avoid erratic behavior due to bit order errors

RESET

: WRITE->

0, Execute software reset of SPI and controllers, reload default register values EXCEPT registers 0x00 and 0x04

1, Set software reset prior to writing ‘0’ to execute the software reset

LONG_INS

: WRITE ->

0, Short (single-byte) instruction word

1, Long (two-byte) instruction word, not necessary since the maximum internal address is REG31 (0x1F)

2X_MODE

: WRITE ->

0, Disable 2x Interpolation Filter

1, Enable 2x Interpolation Filter

FIFO_MODE

: WRITE ->

0, Disable FIFO synchronization

1, Enable FIFO synchronization

DATAFRMT

: WRITE ->

0, Signed input DATA with midscale = 0x0000

1, Unsigned input DATA with midscale = 0x2000

PD

: WRITE ->

0, Enable LVDS Receiver, DAC and Clock Circuitry

1, Power down LVDS Receiver, DAC and Clock Circuitry

REG 01 -> Interrupt Request (IRQ)

Reading REG 01 returns previously written values for all defined register bits unless otherwise noted. Reset value in bold text.

ADR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x01

IRQ

LVDS

SYNC

CROSS

RESV’D

IE_LVDS

IE_SYNC

IE_CROSS

RESV’D

LVDS

: WRITE ->

Don’t Care

: READ ->

0, No active LVDS receiver interrupt

1, Interrupt in LVDS receiver occurred

SYNC

: WRITE ->

Don’t Care

: READ ->

0, No active SYNC logic interrupt

1, Interrupt in SYNC logic occurred

CROSS

: WRITE ->

Don’t Care

: READ ->

0, No active CROSS logic interrupt

1, Interrupt in CROSS logic occurred

IE_LVDS

: WRITE ->

0, Reset LVDS receiver interrupt and disable future LVDS receiver interrupts

1, Enable LVDS receiver interrupt to activate IRQ pin

IE_SYNC

: WRITE ->

0, Reset SYNC logic interrupt and disable future SYNC logic interrupts

1, Enable SYNC logic interrupt to activate IRQ pin

IE_CROSS

: WRITE ->

0, Reset CROSS logic interrupt and disable future CROSS logic interrupts

1, Enable CROSS logic interrupt to activate IRQ pin