AD9736BBC datasheet(20/42 Pages) AD

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AD9736/AD9735/AD9734

Preliminary Technical Data

Rev. PrJ | Page 20 of 42

SHORT INSTRUCTION MODE (8-BIT INSTRUCTION)

The short instruction byte is shown in Table 7.

MSB

LSB

R/W

Table 7. SPI Instruction Byte

R/W

, Bit 7 of the instruction byte, determines whether a read or a

write data transfer will occur after the instruction byte write. Logic

high indicates read operation. Logic 0 indicates a write operation.

N1, N0

, Bits 6 and 5 of the instruction byte, determine the number

of bytes to be transferred during the data transfer cycle. The bit

decodes are shown in Table 8.

A4, A3, A2, A1, A0

, Bits 4, 3, 2, 1, 0 of the instruction byte,

determine which register is accessed during the data transfer

portion of the communications cycle. For multibyte transfers, this

address is the starting byte address. The remaining register

addresses are generated by the AD9736 based on the LSBFIRST bit

(REG00, bit 6).

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

Table 8. Byte Transfer Count

LONG INSTRUCTION MODE (16-BIT INSTRUCTION)

The long instruction bytes are shown in Table 7.

MSB

LSB

I15

I14

I13

I12

I11

I10

R/W

A12

A11

A10

Table 9. SPI Instruction Byte

If LONG_INS = 1 (REG00, bit 4) the instruction byte is extended to

two bytes where the second byte provides an additional 8 bits of

address information. Addresses 0x00 – 0x1F are equivalent in short

and long instruction modes. The AD9736 does not use any

addresses greater than 31 (0x1F) so always set LONG_INS = 0.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK—Serial Clock

. The serial clock pin is used to synchronize

data to and from the AD9736 and to run the internal state

machines. SCLK’s maximum frequency is 20 MHz. All data input

to the AD9736 is registered on the rising edge of SCLK. All data is

driven out of the AD9736 on the rising edge of SCLK.

CSB—Chip Select

. Active low input starts and gates a

communication cycle. It allows more than one device to be used on

the same serial communications lines. The SDO and SDIO pins will

go to a high impedance state when this input is high. Chip select

should stay low during the entire communication cycle.

SDIO—Serial Data I/O

. Data is always written into the AD9736 on

this pin. However, this pin can be used as a bidirectional data line.

The configuration of this pin is controlled by SDIO_DIR at REG00,

bit 7. The default is Logic 0, which configures the SDIO pin as

unidirectional.

SDO—Serial Data Out

. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9736 operates in a single bidirectional I/O mode,

this pin does not output data and is set to a high impedance stat

MSB/LSB TRANSFERS

The AD9736 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by LSBFIRST at REG00, bit 6. The

default is MSB first (LSBFIRST = 0).

When LSBFIRST = 0 (MSB first) the instruction and data bytes

must be written from most significant bit to least significant bit.

Multibyte data transfers in MSB first format start with an

instruction byte that includes the register address of the most

significant data byte. Subsequent data bytes should follow in order

from high address to low address. In MSB first mode, the serial

port internal byte address generator decrements for each data byte

of the multibyte communication cycle.

When LSBFIRST = 1 (LSB first) the instruction and data bytes

must be written from least significant bit to most significant bit.

Multibyte data transfers in LSB first format start with an

instruction byte that includes the register address of the least

significant data byte followed by multiple data bytes. The serial port

internal byte address generator increments for each byte of the

multibyte communication cycle.

The AD9736 serial port controller data address will decrement

from the data address written toward 0x00 for multibyte I/O

operations if the MSB first mode is active. The serial port controller

address will increment from the data address written toward 0x1F

for multibyte I/O operations if the LSB first mode is active.

NOTES ON SERIAL PORT OPERATION

The AD9736 serial port configuration is controlled by REG00, bits

4, 5, 6 and 7. It is important to note that the configuration changes

immediately upon writing to the last bit of the register. For

multibyte transfers, writing to this register may occur during the

middle of communication cycle. Care must be taken to compensate

for this new configuration for the remaining bytes of the current

communication cycle. The same considerations apply to setting the

software reset, RESET (REG00, bit 5). All registers are set to their

default values EXCEPT REG00 and REG04 which remain

unchanged.

Use of only single byte transfers when changing serial port

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