LT4351CMS datasheet(5/20 Pages) LINER

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LT4351

sn4351 4351fs

PI FU CTIO S

GATE (Pin 1): MOSFET Gate Drive Pin. This pin is tied to

the gate(s) of the external N-channel MOSFET(s). The

GATE pin drives high when UV is above the VUV(TH)

threshold, OV is below the VOV(TH) threshold and VIN is

greater than OUT by 15mV. When not driven high, GATE

actively pulls to GND. GATE can sink or source up to

600mA.

VDD (Pin 2): Gate Drive Supply Pin. This is the supply pin

for the gate drive amplifier. It is either generated by the

onboard boost regulator or supplied externally. When

turning on the MOSFET(s), a large high current pulse flows

through this pin. Bypass the pin with a 1

µF capacitor

placed in close proximity to the part. The voltage on this

pin is also the feedback for the boost regulator. If the VDD

voltage exceeds the VIN voltage by 10.7V, the boost switch

is held off.

VIN (Pin 3): Input Supply Pin. This pin is the supply pin for

the control circuitry and the boost regulator. It is also one

input in conjunction with OUT for controlling the

MOSFET(s). Bypassing should include a low ESR/ESL

capacitor placed in close proximity to the part.

SW (Pin 4): Boost Regulator Switch Pin. This pin is the

boost regulator switch output. It is connected to the boost

inductor and the boost diode. Peak switch current is

limited internally to 450mA. If an external VDD supply is

used, leave this pin open.

GND (Pin 5): Device Ground Pin. This pin is ground for the

boost switch, gate driver as well as the control circuitry.

Tie the VIN and VDD bypass capacitors and ground plane

close to this pin to minimize the effects of switching

currents on part performance.

Typical SW Pin Waveform

SW Pin Waveform at Maximum

Boost Regulator Output

VSW

5V/DIV

VIN = 5V

µs/DIV

3451 G12

4.7

µH INDUCTOR

VSW

5V/DIV

VIN = 5V

µs/DIV

3451 G13

4.7

µH INDUCTOR

TYPICAL PERFOR A CE CHARACTERISTICS

Specifications are at TA = 25°C unless otherwise specified.

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