LT4351CMS datasheet(15/20 Pages) LINER

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LT4351

sn4351 4351fs

APPLICATIO S I FOR ATIO

The die junction temperature is then computed as:

TJ = TA + θJA • PTOTAL

where TJ is the die junction temperature, TA is the ambient

temperature,

θJA is the thermal resistance of the part

(120

°C/W) and PTOTAL is ascertained from the above.

Therefore, a 0.1W power dissipation causes a 12 degree

temperature rise above ambient.

Design Example

The following demonstrates the calculations involved for

setting design components for a 5V system that requires

5A. Two supplies are used to do this. The VIN supply will

be deemed in spec when it is within

±5% of nominal. Allow

5% of hysteresis for UV.

So,

UVFAULT = 4.75V, UVHYST = 0.25V

OVFAULT = 5.5

Two separate resistive dividers are used.

For the UV divider:

k Use

HYST

UVHYST

FAULT

025

24 9

249

475

0 3

()

•

–

.• .

.– .

R1 = 1.68k. The closest 1% value is 1.69k

Figure 14. Total Power (Typical)

Figure 13. PGATE vs VIN (VDD = VIN + 10.7)

The OV resistors are set as a straight resistive divider.

If the current in the RA, RB divider is 200

µA, then:

FAULT

= 







= 







0.3V

200 A

1.5k use 1.47k (1%)

then

25.48k use 25.5k

–

–.

11 47

For regulation, the MOSFETs must have:

DS <=

Ω

•

This very low value cannot be accomplished with a single

set of MOSFETs so a decision must be made whether to

use multiple MOSFETs or to live with an unregulated

offset. Since low m

Ω RDS(ON) is available, the IR drop

using a single FET would still be acceptable. For RDS(ON) =

Ω the drop is 2 • 5A • 4mΩ = 40mV. The finished

schematic is shown in Figure 15.

VIN (V)

0.002

0.003

4351 F13

0.001

0.004

fGATE = 1kHz

QG = 50nC

VIN (V)

0.10

0.12

4351 F14

0.08

0.06

0.16

0.14

L = 10

µH

L = 4.7

µH

VDD = VIN + 10

0.5mA GATE CURRENT

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