AD9239 datasheet(24/41 Pages) AD

24 / 41 page

Data Sheet

AD9239

Rev. E | Page 23 of 40

Digital Start-Up Sequence

The output digital data from the AD9239 is coded and packetized,

which requires the device to have a certain start-up sequence.

A specific set of procedures must be initialized by the user to

capture coherent data at the receiving logic and optionally

minimize skew and time misalignment.

Minimize Skew and Time Misalignment (Optional)

To minimize skew and time misalignment between each

channel of the digital outputs, take the following actions to

ensure that each channel data packet is within ±1 clock cycle of

its specified switching time. For some receiver logic, this is not

required.

Power down the device fully through the external PDWN pin.

Perform a chip reset via the external RESET pin.

Power up the device by releasing the external PDWN pin.

Link Initialization (Required)

Initialize a soft reset via Bit 5 of Register 0 (see Table 16).

All PGMx pins are automatically initialized as sync pins by

default. Use these pins to lock the FPGA timing and data

capture during initial startup. These pins are respective to

each channel (PGM3 = Channel A).

Each sync pin is held low until its respective PGMx pin

receives a high signal input from the receiver, during which

time the ADC outputs a training pattern. The training

pattern values are shown in Table 9. These values can also

be read back via the SPI in Register 19 through Register 20.

When the receiver finds the frame boundary, the sync

identification is deasserted high via the sync pin or via an

SPI write. The ADC outputs the valid data on the next packet

boundary. The time necessary for sync establishment is highly

dependent on the receiver logic processing. Refer to the

Switching Specifications section; the switching timing is

directly related to the ADC channel.

When the device reaches steady state operation, the PGMx

pins can each be assigned to be a standby option by using

sync pins.

Table 9. Training Pattern for Link Initialization

Training Pattern

Pattern LSB

Pattern MSB

0xA5

0x66

0x53

0x35

0xBB

0xDD

0xAA

0xCC

Digital Outputs and Timing

The AD9239 has differential digital outputs that power up on

default. The driver current is derived on chip and sets the output

current at each output equal to a nominal 4 mA. Each output

presents a 100 Ω dynamic internal termination to reduce unwanted

reflections.

A 100 Ω differential termination resistor should be placed at each

receiver input to result in a nominal 400 mV p-p swing at the

receiver. Alternatively, single-ended 50 Ω termination can be

used. When single-ended termination is used, the termination

voltage should be DRVDD/2; otherwise, ac coupling capacitors

can be used to terminate to any single-ended voltage.

The AD9239 digital outputs can interface with custom application-

specific integrated circuits (ASICs) and field-programmable gate

array (FPGA) receivers, providing superior switching performance

in noisy environments. Single point-to-point net topologies are

recommended with a single differential 100 Ω termination resistor

placed as close to the receiver logic as possible. The common mode

of the digital output automatically biases itself to half the supply

of DRVDD if dc-coupled connecting is used. For receiver logic

that is not within the bounds of the DRVDD supply, an ac-coupled

connection should be used. Simply place a 0.1 μF capacitor on

each output pin and derive a 100 Ω differential termination

close to the receiver side.

If there is no far-end receiver termination or there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than 6 inches and that the differential output traces be close

together and at equal lengths.

100Ω

DIFFERENTIAL

TRACE PAIR

DOUT + x

DRVDD

DOUT – x

VCM = DRVDD/2

OUTPUT SWING = 400mV p-p

RECEIVER

Figure 61. DC-Coupled Digital Output Termination Example

100Ω

DIFFERENTIAL

TRACE PAIR

DOUT + x

DRVDD

VRXCM

DOUT – x

VCM = Rx VCM

OUTPUT SWING = 400mV p-p

0.1µF

RECEIVER

Figure 62. AC-Coupled Digital Output Termination Example

AD9239 датащи(PDF) 24 Page - Analog Devices

AD9239 датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL