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AD7992

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PRELIMINARYTECHNICAL DATA

CYCLE TIMER REGISTER

The Cycle Timer Register is a 8-bit read/write register,

which stores the conversion interval value for the Auto-

matic Cycle mode of the AD7992, see Modes of Opera-

tion section. Bits D3 - D5 of the Cycle Timer Register are

unused and should contain 0’s at all times. On power up,

the Cycle Timer Register will contain all 0s, thus dis-

abling the Automatic Cycle operation of the AD7992. To

enable the Automatic Cycle Mode the user must write to

the Cycle Timer Register, selecting the required conver-

sion interval. Table XIIa shows the structure of the Cycle

Timer register while Table XIIb shows how the bits in

this register are decoded to provide various automatic

sampling intervals.

Table XIIa.

Cycle Timer Register

Sample Bit Trial 0

Cyc*

Cyc*Cyc*

Dealy

Delay

Bit2

Bit1 Bit0

*Default settings at Power-up

Table XIIb.

Cycle Timer Intervals

CYC Reg Value(D2,D1,D0)

Conversion Interval

000

Mode not selected

001

TCONVERT x 32

010

TCONVERT x 64

011

TCONVERT x 128

100

TCONVERT x 256

101

TCONVERT x 512

110

TCONVERT x 1024

111

TCONVERT x 2048

ALERT STATUS REGISTER

The Alert Status Register is a 8-bit read/write register, of

which only the four LSBs are used. This register provides

information on an Alert event. If a conversion results in

activating the ALERT pin or the Alert_Flag bit in the

Conversion Result Register, as described in the Limit

Registers section, then the Alert Status Register may be

read to gain further information. It contains 2 status bits

per channel, one corresponding to the DATAHIGH limit

and the other to the DATALOW limit. Whichever bit has a

status of 1 will show where the violation occured, i.e. on

which channel and whether on upper or lower limit. If a

second alert event occurs on the other channel between

receiving the first alert and interrogating the Alert Status

be set also.

The entire contents of the Alert Status register may be

cleared by writing 1,1, to bits D2 and D1 in the Configu-

ration register as shown in Table VI. This may also be

acheived by ‘writing’ all 1’s to the Alert Status Register

itself. This means that if the Alert Status Register is ad-

dressed for a write which is all 1’s, then the contents of the

Alert Status Register will then be cleared or resest to all

0’s. Alternatively, an individual active Alert bit(s) may be

reset within the Alert Status Register by performing a

write of ‘1’ to that bit alone. The advantage of this is that

once an Alert event has been serviced, that particular bit

can be reset, e.g. CH1LO, without clearing the entire con-

tents of the Alert Status Register, thus preserving the status

of any additional Alert, e.g. CH2HI, which has occured

while servicing the first. If it is not necessary to clear an

Alert directly after servicing then obviously the Alert Sta-

tus register may be read again immediately to look for any

new Alerts, bearing in mind that the one just serviced will

still be active.

Table XIa. Alert Status Register

000

CH2HI CH2LO CH1HI

CH1LO

Table XIb. Alert Status Register Bit Function

Description

Bit Mnemonic Comment

D 0 CH1LO

Violation of DATALOW limit on Channel

1 if this bit set to 1, no violation if 0.

D 1 CH1HI

Violation of DATAHIGH limit on Chan

nel 1 if this bit set to 1, no violation if 0.

D 2 CH2LO

Violation of DATALOW limit on Channel

2 if this bit set to 1, no violation if 0.

D 3 CH2HI

Violation of DATAHIGH limit on Chan

nel 2 if this bit set to 1, no violation if 0.

TCONVERT is equivalent to the conversion time of the ADC.

It is recommended that no I2C Bus activity occurs when a

conversion is taking place. However if this is not possible,

e.g. when operating in Mode 2 or the Automatic Cycle

mode, therefore in order to maintain the performance of

the ADC, Bits D7 and D6 in the cycle timer register are

used to delay critical sample intervals and bit trials from

occurring while there is activity on the I2C Bus. This may

have the effect of increasing the Conversion time. When

bits D7 and D6 are both 0, the bit trial and sample inter-

val delaying mechanism will be implemented. The default

setting of D7 and D6 is 0. However if bit trial delays

extend longer than 1 µs the conversion will terminate.

When D7 is 0 the Sampling instant delay will be imple-

mented. When D6 is 0 the bit trial delay will be imple-

mented. To turn off both set D7 and D6 to 1.

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