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AD7992

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PRELIMINARYTECHNICAL DATA

HYSTERESIS REGISTER (CH1/CH2)

The Hysteresis Register is a 16-bit read/write register, of

which only the 12 LSBs of the Register are used. The

registers. Each pair of Limit registers has a dedicated hys-

teresis register. The hysteresis value determines the reset

point for the ALERT pin/Alert_Flag if a violation of the

limits has occurred. If a hysteresis value of say 8 LSBs is

required on the upper and lower limits of channel 1 then

the 12 bit word, 0000 0000 0000 1000, should be written

to Hysteresis Register CH1, the address of which is shown

in Table III. On power up, the Hysteresis Registers will

contain a value of 8 LSBs. If a different hysteresis value is

required then that value must be written to the Hysteresis

Table Xa.

Hysteresis Register (First Read/Write)

D15

D14

D13 D12

D11

D10

Alert_Flag 0

B11

B10

B 9

B 8

Table Xb.

Hysteresis Register (Second Read/Write)

Using the Limit Registers to Store Min/Max Conversion

Results

If fullscale, i.e. all 1s, are written to the Hysteresis regis-

ter for a channel then the DATAHIGH and DATALOW Reg-

isters for that channel will no longer act as Limit registers

as previously described, but instead they will act as storage

registers for the maximum and minimum conversion re-

sults returned from conversions on a channel over any

given period of time. This function is useful in applica-

tions where the widest span of actual conversion results is

required rather than using the ALERT to signal an inter-

vention is necessary, e.g. monitoring temperature ex-

tremes during refrigerated goods transportation.

It must be noted that on power-up, the contents of the

DATAHIGH register for each channel will be fullscale,

while the contents of the DATALOW registers will be

zeroscale by default so minimum and maximum conver-

sion values being stored in this way will be lost if power is

removed or cycled.

When using the limit registers to store the min and max

conversion results, the Alert_Flag bit in the limit regis-

ters, D15, is used to indicate that an alert has happened on

the other Input channel. If the Alert_Flag bit is set to 1, it

will be reset when the Conversion result returns to a value

at least N LSBs above the DATALOW Register value or

below the DATAHIGH Register value or if bits D2 and D1

of the Configuration Register are set to 1.

The Limit Registers can be used to monitor the conver-

sion results on one or both channels. The AD7992 will

signal an Alert (in either hardware or software or both

depending on configuration) if the result moves outside

the upper or lower limit set by the user.

DATAHIGH REGISTER CH1/CH2

The DATAHIGH Register for a channel is a 16-bit read/

write register, of which only the 12 LSBs are used. The

ALERT output and/or the Alert_Flag bit in the Conver-

sion Result Register. If the value in the Conversion Result

ter, then the Alert_Flag bit is set to 1 and the ALERT pin

is activated (the latter is true if ALERT is enabled in the

Configuration Register). When the conversion result re-

turns to a value at least N LSBs below the DATAHIGH

will be reset. The value of N is taken from the 12-bit

Hysteresis register associated with that channel.

The

ALERT pin can also be reset by writing to bits D2,D1 in

the Configuration Register.

Table VIIIa.

DATAHIGH Register (First Read/Write)

D15

D14

D13 D12

D11

D10

Alert_Flag 0

B11

B10

B 9

B 8

Table VIIIb.

DATAHIGH Register (Second Read/Write)

DATALOW REGISTER CH0/CH1

The DATALOW Register for a channel is a 16-bit read/

write register, of which only the 12 LSBs are used. The

ALERT output and/or the Alert_Flag bit in the conver-

sion result register. If the value in the Conversion Result

then the Alert_Flag bit is set to 1 and the ALERT pin is

activated (the latter is true if ALERT is enabled in the

Configuration Register). When the Conversion result re-

turns to a value at least N LSBs above

the DATALOW

will be reset. The value of N is taken from the 12-bit

Hysteresis register associated with that channel.

The

ALERT pin can also be reset by writing to bit D2,D1 in

the Configuration Register.

Table IXa.

DATALOW Register (First Read/Write)

D15

D14

D13 D12

D11

D10

Alert_Flag 0

B11

B10

B 9

B 8

Table IXb.

DATALOW Register (Second Read/Write)

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