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AD7771 датащи(PDF) 12 Page - Analog Devices

номер детали AD7771
подробное описание детали  8-Channel, 24-Bit, Simultaneous Sampling ADC
PDF  99 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD7771 датащи(HTML) 12 Page - Analog Devices

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Data Sheet
AD7771
Rev. 0 | Page 11 of 98
SYNCHRONIZATION PINS AND RESET TIMING CHARACTERISTICS
AVDD1x = 1.65 V, AVSSx1 = −1.65 V (dual supply operation), AVDD1x = 3.3 V, AVSSx = AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V;
IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− = 2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX,
unless otherwise noted.
Table 4.
Parameter
Description2
Test Conditions/Comments
Min
Typ
Max
Unit
t26
START setup time
10
ns
t27
START hold time
MCLK
ns
t28
MCLK falling edge to SYNC_OUT falling edge
MCLK
ns
t29
SYNC_IN setup time
10
ns
t30
SYNC_IN hold time
MCLK
ns
tINIT_SYNC_IN
SYNC_IN rising edge to first DRDY
16 kSPS, high resolution mode
145
µs
tINIT_RESET
RESET rising edge to first DRDY
16 kSPS, high resolution mode
225
µs
t31
RESET hold time
2 × MCLK
ns
tPOWER_UP
Start time
tPOWER_UP is not shown in Figure 4
2
ms
1
AVSSx refers to the following pins: AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4. This term is used throughout the data sheet.
2
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
START
SYNC_OUT
SYNC_IN
DRDY
RESET
t26
t27
t28
t29
tINIT_SYNC_IN
t31
tINIT_RESET
t30
Figure 4. Synchronization Pins and Reset Control Interface Timing Diagram



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