AD7761BSTZ datasheet(19/76 Pages) AD

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AD7761

Data Sheet

Rev. A | Page 18 of 75

Pin No.

Mnemonic

Type1

Description

XTAL2/MCLK

Input 2 for CMOS or Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this

configuration.

External crystal. XTAL2 is connected to the external crystal. In SPI control mode, when using a

crystal source, the FILTER pin must be set to Logic 1 for correct operation.

LVDS. A second LVDS input is connected to this pin.

CMOS clock. This pin operates as an MCLK input. CMOS input with logic level of IOVDD/DGND.

Set FILTER pin to Logic 1 for crystal clock source.

DGND

Digital Ground. This pin is nominally 0 V.

DREGCAP

Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a high quality,

low equivalent series resistance (ESR), 10 µF capacitor. For optimum performance, use a

decoupling capacitor with an ESR specification between 50 mΩ and 400 mΩ. This pin is not for

use in circuits external to the AD7761. For 1.8 V IOVDD operation, connect this pin to IOVDD via

an external trace to provide power to the digital processing core.

IOVDD

Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the digital

processing core via the digital LDO when IOVDD is at least 2.25 V. For 1.8 V IOVDD operation,

connect this pin to DREGCAP via an external trace to provide power to the digital processing core.

SYNC_IN

Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. It is used in

the synchronization of any AD7761 that requires simultaneous sampling or is in a daisy chain.

Ignore the START and SYNC_OUT functions if the SYNC_IN pin is connected to the system

synchronization pulse. This signal pulse must be synchronous to the MCLK clock domain.

START

Start Signal. The START pulse synchronizes the AD7761 to other devices. The signal can be

asynchronous. The AD7761 samples the input and then outputs a SYNC_OUT pulse.

This SYNC_OUT pulse must be routed to the SYNC_IN pin of this device and any other AD7761

devices that must be synchronized together. This means that the user does not need to run the

ADCs and their digital host from the same clock domain, which is useful when there are long

traces or back planes between the ADC and the controller. If this pin is not used, it must be tied

to a Logic 1 through a pull-up resistor.

SYNC_OUT

Synchronization Output. This pin operates only when using the START input. When using

the START input feature, the SYNC_OUT pin must be connected to SYNC_IN via an external

trace. SYNC_OUT is a digital output that is synchronous to the MCLK signal; the synchronization

signal driven in on START is internally synchronized to the MCLK signal and is driven out

on SYNC_OUT. SYNC_OUT can also be routed to other AD7761 devices requiring simultaneous

sampling and/or daisy-chaining, ensuring synchronization of devices related to the MCLK clock

domain. It must then be wired to drive the SYNC_IN pin on the same AD7761 and on the other

AD7761 devices.

AIN7+

Positive Analog Input to ADC Channel 7.

AIN7−

Negative Analog Input to ADC Channel 7.

AIN6+

Positive Analog Input to ADC Channel 6.

AIN6−

Negative Analog Input to ADC Channel 6.

REF2+

Reference Input Positive. REF2+ is the positive reference terminal for Channel 4 to Channel 7.

The REF2+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external reference differential

between REF2+ and REF2− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to AVSS

with a high quality capacitor, and maintain a low impedance between this capacitor and Pin 46.

REF2−

Reference Input Negative. REF2− is the negative reference terminal for Channel 4 to Channel 7. The

REF2− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality

capacitor, and maintain a low impedance between this capacitor and Pin 46.

AVDD1B

Analog Supply Voltage. This pin is 5 V ± 10% with respect to AVSS.

AVSS1B

Negative Analog Supply. This pin is nominally 0 V.

AIN5+

Positive Analog Input to ADC Channel 5.

AIN5−

Negative Analog Input to ADC Channel 5.

AIN4+

Positive Analog Input to ADC Channel 4.

AIN4−

Negative Analog Input to ADC Channel 4.

AVSS2B

Negative Analog Supply. This pin is nominally 0 V.

REGCAPB

Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.

AVDD2B

Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.

AVSS

Negative Analog Supply. This pin is nominally 0 V.

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