AD7761BSTZ datasheet(39/76 Pages) AD

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AD7761

Data Sheet

Rev. A | Page 38 of 75

START

SYNC_IN

DOUT0

DOUT1

DRDY

MCLK

SPI INTERFACE

SYNC_OUT

DSP/

FPGA

AD7761

SYNCHRONIZATION

LOGIC

DIGITAL FILTER

MASTER

CLOCK

IOVDD

Figure 55. Connection Diagram for Synchronization Using SPI_SYNC

The SYNC_OUT pin can also be routed to the SYNC_IN pins of

other AD7761 devices, allowing simultaneous sampling to occur

across larger channel count systems. Any daisy-chained system of

AD7761 devices requires that all ADCs be synchronized.

In a daisy-chained system of AD7761 devices, two successive

synchronization pulses must be applied to guarantee that all

ADCs are synchronized. Two synchronization pulses are also

required in a system of more than one AD7761 device sharing a

single MCLK signal, where the DRDY pin of only one device is

used to detect new data.

As per any synchronization pulse present on the SYNC_IN pin,

the digital filters of the AD7761 are reset by the SPI_SYNC

command. The full settling time of the filters must then elapse

before valid data is output on the data interface.

Analog Input Precharge Buffers

The AD7761 contains precharge buffers on each analog input to

ease the drive requirements on the external amplifier. Each analog

input precharge buffer can be enabled or disabled using the analog

input precharge buffer registers (see Table 48 and Table 49).

When writing to these registers, the user must write the inverse

of the required bit settings. For example, to clear Bit 1 of this

Bit 1 and sets all other bits. If the user reads the register again

after writing 0x01, the data read is 0xFE, as required.

Reference Precharge Buffers

The AD7761 contains reference precharge buffers on each

reference input to ease the drive requirements on the external

reference and help to settle any nonlinearity on the reference

inputs. Each reference precharge buffer can be enabled or

disabled using the reference precharge buffer registers (see

Table 50 and Table 51).

Per Channel Calibration Gain, Offset, and Sync Phase

The user can adjust the gain, offset, and sync phase of the

AD7761. These options are available only in SPI control mode.

Further register information and calibration instructions are

available in the Offset Registers section, the Gain Registers section,

and the Sync Phase Offset Registers section. See the Calibration

section for information on calibration equations.

GPIOs

The AD7761 has five GPIO pins available when operating in SPI

control mode. For further information on GPIO configuration,

see the GPIO Functionality section.

SPI CONTROL MODE EXTRA DIAGNOSTIC

FEATURES

RAM Built In Self Test

The read only memory (RAM) built in self test (BIST) is a

coefficient check for the digital filters. The AD7761 DSP path uses

some internal memories for storing data associated with filtering

and calibration. A user may, if desired, initiate a built in self test

(BIST) of these memories. Normal conversions are not possible

while BIST is running. The test is started by writing to the BIST

control register, Register 0x08. The results and status of the test are

available in the status register, Register 0x09 (see Table 43).

Normal ADC conversion is disrupted when this test is run. A

synchronization pulse is required after this test is complete to

resume normal ADC operation.

Revision Identification Number

The AD7761 contains an identification register that is accessible

in SPI control mode, the revision identification register. This

serial control interface. Register information is available in the

Revision Identification Register section.

Diagnostic Meter Mode

The diagnostic metering mode can be used to verify the

functionality of each ADC by internally passing a positive full-

scale, midscale, or negative full-scale voltage to the ADC. The

user can then read the resulting ADC conversion result to

determine that the ADC is operating correctly. To configure

ADC conversion diagnostics, see the ADC Diagnostic Receive

Select Register section and the ADC Diagnostic Control

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