AD7761BSTZ datasheet(43/76 Pages) AD

43 / 76 page

AD7761

Data Sheet

Rev. A | Page 42 of 75

REFERENCE INPUT

The AD7761 has two differential reference input pairs. REF1+

and REF1− are the reference inputs for Channel 0 to Channel 3,

and REF2+ and REF2− are for Channel 4 to Channel 7. The

absolute input reference voltage range is 1 V to AVDD1 − AVSS.

Like the analog inputs, the reference inputs have a precharge buffer

option. Each ADC has an individual buffer for each REFx+ and

REFx−. The precharge buffers help reduce the burden on the

external reference circuitry.

In pin control mode, the reference precharge buffers are off by

default. In SPI control mode, the user can enable or disable the

reference precharge buffers. In the case of unipolar analog supplies,

in SPI control mode, the user can achieve the best performance and

power efficiency by enabling only the REFx+ buffers. The reference

input current scales linearly with the modulator clock rate.

For 32 MHz MCLK and MCLK/4 fast mode, the differential

input current is ~72 µA/V per channel, unbuffered, and

~16 µA/V per channel with the precharge buffers enabled.

With the precharge buffers off, REFx+ = 5 V, and REFx− = 0 V,

REFx± = 5 V × 72 µA/V = 360 µA

With the precharge buffers on, REFx+ = 5 V, and REFx− = 0 V,

REFx± = 5 V × 16 µA/V = 80 µA

For the best performance and headroom, it is recommended to

use a 4.096 V reference such as the ADR444 or the ADR4540.

For the best performance at high sampling rates, it is recommended

to use an external reference drive amplifier such as the ADA4841-1

or the AD8031. Figure 62 shows a configuration diagram of the

reference connection.

REFx+

REFx–

AD7761

ADA4841-1

VOUT

VIN

ADR4540

Figure 62. Typical Reference Input Configuration Diagram

CLOCK SELECTION

The AD7761 has an internal oscillator used for initial power-up

of the device. After the AD7761 completes the start-up routine,

the device normally transfer control of the internal clocking to

the externally applied MCLK. The AD7761 counts the falling

edges of the external MCLK over a given number of internal clock

cycles to determine if the clock is valid and at least a frequency of

1.15 MHz. If there is a fault with the external MCLK, the transfer of

control does not occur, the AD7761 outputs an error in the

status header, and the clock error bit is set in the device status

exit this error state.

Three clock source input options are available to the AD7761:

external CMOS, crystal oscillator, or LVDS. The clock is selected on

power-up and is determined by the state of the CLK_SEL pin.

If CLK_SEL = 0, the CMOS clock option is selected and the

clock is applied to Pin 32 (Pin 31 is tied to DGND).

If CLK_SEL = 1, the crystal or LVDS option is selected and the

crystal or LVDS is applied to Pin 31 and Pin 32. The LVDS

option is available only in SPI control mode. An SPI write to

Bit 3 of Register 0x04 enables the LVDS clock option.

DIGITAL FILTERING

The AD7761 offers two types of digital filters. In SPI control

mode, these filters can be chosen on a per channel basis. In pin

control mode, only one filter can be selected for all channels. The

digital filters available on the AD7761 are

•

Sinc5 low latency filter, −3 dB at 0.204 × ODR

•

Wideband low ripple filter, −3 dB at 0.433 × ODR

Both filters can be operated in one of six different decimation rates,

allowing the user to choose the optimal input bandwidth and speed

of the conversion vs. the desired power mode or resolution.

Sinc5 Filter

Most precision Σ-Δ ADCs use a sinc filter. The sinc5 filter offered

in the AD7761 enables a low latency signal path useful for dc

inputs, for control loops, or where other specific postprocessing

is required. The sinc5 filter path offers the lowest noise and power

consumption. The sinc5 filter has a −3 dB BW of 0.204 × ODR.

Table 11 contains the noise performance for the sinc5 filter across

power modes and decimation ratios.

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

NORMALIZED INPUT FREQUENCY (

fIN/fODR)

Figure 63. Sinc5 Filter Frequency Response (Decimation = ×32)

The settling times for the AD7761 when using the sinc5 filter are

shown in Table 26.

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