CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 2 of 58
TABLE OF CONTENTS
1.0 FEATURES ...................................................................................................................................... 6
2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 7
2.1 GPIO ........................................................................................................................................... 7
2.2 DAC ............................................................................................................................................ 7
2.3 Clock ........................................................................................................................................... 7
2.4 Memory ....................................................................................................................................... 7
2.5 Power-on Reset, Watchdog, and Free-running Time ................................................................. 7
2.6 I2C and HAPI Interface ............................................................................................................... 7
2.7 Timer ........................................................................................................................................... 7
2.8 Interrupts ..................................................................................................................................... 8
2.9 USB ............................................................................................................................................. 8
3.0 PIN CONFIGURATIONS ................................................................................................................ 10
4.0 PRODUCT SUMMARY TABLES ................................................................................................... 11
4.1 Pin Assignments ....................................................................................................................... 11
4.2 I/O Register Summary .............................................................................................................. 11
4.3 Instruction Set Summary ........................................................................................................... 13
5.0 PROGRAMMING MODEL .............................................................................................................. 14
5.1 14-bit Program Counter (PC) .................................................................................................... 14
5.1.1 Program Memory Organization
..................................................................................................... 15
5.2 8-Bit Accumulator (A) ................................................................................................................ 16
5.3 8-Bit Temporary Register (X) .................................................................................................... 16
5.4 8-Bit Program Stack Pointer (PSP) ........................................................................................... 16
5.4.1 Data Memory Organization ............................................................................................................. 16
5.5 8-Bit Data Stack Pointer (DSP) ................................................................................................. 16
5.6 Address Modes ......................................................................................................................... 17
5.6.1 Data (Immediate) ............................................................................................................................ 17
5.6.2 Direct ............................................................................................................................................... 17
5.6.3 Indexed ........................................................................................................................................... 17
6.0 CLOCKING ..................................................................................................................................... 17
7.0 RESET ............................................................................................................................................ 18
7.1 Power-on Reset ........................................................................................................................ 18
7.2 Watchdog Reset ....................................................................................................................... 18
8.0 SUSPEND MODE ........................................................................................................................... 19
9.0 GENERAL-PURPOSE I/O (GPIO) PORTS .................................................................................... 19
9.1 GPIO Configuration Port ........................................................................................................... 20
9.2 GPIO Interrupt Enable Ports ..................................................................................................... 21
10.0 DAC PORT ................................................................................................................................... 22
10.1 DAC Isink Registers ................................................................................................................ 23
10.2 DAC Port Interrupts ................................................................................................................. 23
11.0 12-BIT FREE-RUNNING TIMER .................................................................................................. 24
12.0 I2C AND HAPI CONFIGURATION REGISTER ............................................................................ 24
13.0 I2C-COMPATIBLE CONTROLLER .............................................................................................. 25
14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ........................................................ 27
15.0 PROCESSOR STATUS AND CONTROL REGISTER ................................................................ 28
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