CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 4 of 58
LIST OF FIGURES
Figure 5-1. Program Memory Space with Interrupt Vector Table ......................................................... 15
Figure 6-1. Clock Oscillator On-Chip Circuit ......................................................................................... 17
Figure 7-1. Watchdog Reset ................................................................................................................. 18
Figure 9-1. Block Diagram of a GPIO Pin ............................................................................................. 19
Figure 9-2. Port 0 Data ......................................................................................................................... 20
Figure 9-3. Port1 Data .......................................................................................................................... 20
Figure 9-4. Port 2 Data ......................................................................................................................... 20
Figure 9-5. Port 3 Data ......................................................................................................................... 20
Figure 9-6. GPIO Configuration Register .............................................................................................. 20
Figure 9-7. Port 0 Interrupt Enable ....................................................................................................... 21
Figure 9-8. Port 1 Interrupt Enable ....................................................................................................... 22
Figure 9-9. Port 2 Interrupt Enable ....................................................................................................... 22
Figure 9-10. Port 3 Interrupt Enable ..................................................................................................... 22
Figure 10-1. Block Diagram of a DAC Pin ............................................................................................ 22
Figure 10-2. DAC Port Data .................................................................................................................. 23
Figure 10-3. DAC Sink Register ........................................................................................................... 23
Figure 10-4. DAC Port Interrupt Enable ................................................................................................ 23
Figure 10-5. DAC Port Interrupt Polarity ............................................................................................... 23
Figure 11-3. Timer Block Diagram ........................................................................................................ 24
Figure 11-1. Timer LSB Register .......................................................................................................... 24
Figure 11-2. Timer MSB Register ......................................................................................................... 24
Figure 12-1. HAPI/I2C Configuration Register ...................................................................................... 24
Figure 13-1. I2C Data Register .............................................................................................................. 25
Figure 13-2. I2C Status and Control Register ....................................................................................... 25
Figure 15-1. Processor Status and Control Register ............................................................................ 28
Figure 16-1. Global Interrupt Enable Register ...................................................................................... 29
Figure 16-2. USB Endpoint Interrupt Enable Register .......................................................................... 29
Figure 16-3. Interrupt Controller Function Diagram .............................................................................. 30
Figure 16-4. GPIO Interrupt Structure .................................................................................................. 32
Figure 18-1. Hub Ports Connect Status ................................................................................................ 34
Figure 18-2. Hub Ports Speed .............................................................................................................. 35
Figure 18-3. Hub Ports Enable Register ............................................................................................... 35
Figure 18-4. Hub Downstream Ports Control Register ......................................................................... 36
Figure 18-5. Hub Ports Force Low Register ......................................................................................... 36
Figure 18-6. Hub Ports Force Low Register ......................................................................................... 36
Figure 18-7. Hub Ports SE0 Status Register ........................................................................................ 36
Figure 18-8. Hub Ports Data Register .................................................................................................. 37
Figure 18-9. Hub Ports Suspend Register ............................................................................................ 37
Figure 18-10. Hub Ports Resume Status Register ............................................................................... 37
Figure 18-11. USB Status and Control Register ................................................................................... 38
Figure 19-1. USB Device Address Registers ........................................................................................ 39
Figure 19-2. USB Device Endpoint Zero Mode Registers .................................................................... 40
Figure 19-3. USB Non-Control Device Endpoint Mode Registers ........................................................ 41
Figure 19-4. USB Endpoint Counter Registers ..................................................................................... 41
Figure 19-5. Token/Data Packet Flow Diagram ....................................................................................43
Figure 22-1. Sample Schematic ........................................................................................................... 51
Figure 25-1. Clock Timing ..................................................................................................................... 54
Figure 25-2. USB Data Signal Timing ................................................................................................... 54
Figure 25-3. HAPI Read by External Interface from USB Microcontroller ............................................ 54
Figure 25-4. HAPI Write by External Device to USB Microcontroller .................................................... 55
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