48 / 58 page
CY7C66013
CY7C66113
Document #: 38-08024 Rev. *A
Page 48 of 58
(STALL[4] =
0)
1
1
0
1
Out
x
UC
x
UC
UC
UC
UC
UC UC
UC
NoChange stall
no
(STALL[4] =
1)
1
1
0
1
In
x
UC
x
UC
UC
UC
UC
1
UC
1
1 1 0 0 ACK (back) yes
NAK In/erroneous Out
1
1
0
0
Out
x
UC
x
UC
UC
UC
UC
UC UC
UC
NoChange ignore
no
1
1
0
0
In
x
UC
x
UC
UC
UC
UC
1
UC
UC
NoChange NAK
yes
Isochronous endpoint (In)
0
1
1
1
Out
x
UC
x
UC
UC
UC
UC
UC UC
UC
NoChange ignore
no
0
1
1
1
In
x
UC
x
UC
UC
UC
UC
1
UC
UC
NoChange TX
yes
21.0
Register Summary
Addr
ess
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/Write
/Both[5, 6, 7]
Default/
Reset
0x00 Port 0 Data
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
bbbbbbbb
1111111
1
0x01 Port 1 Data
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
bbbbbbbb
1111111
1
0x02 Port 2 Data
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
bbbbbbbb
1111111
1
0x03 Port 3 Data
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
bbbbbbbb
1111111
1
0x04 Port 0 Interrupt
Enable
P0.7 Intr
Enable
P0.6 Intr
Enable
P0.5 Intr
Enable
P0.4 Intr
Enable
P0.3 Intr
Enable
P0.2 Intr
Enable
P0.1 Intr
Enable
P0.0 Intr
Enable
wwwwwww
w
000000
00
0x05 Port 1 Interrupt
Enable
P1.7 Intr
Enable
P1.6 Intr
Enable
P1.5 Intr
Enable
P1.4 Intr
Enable
Reserve
d
P1.2 Intr
Enable
P1.1 Intr
Enable
P1.0 Intr
Enable
wwwwwww
w
000000
00
0x06 Port 2 Interrupt
Enable
P2.7 Intr
Enable
P2.6 Intr
Enable
P2.5 Intr
Enable
P2.4 Intr
Enable
P2.3 Intr
Enable
Reserve
d
Reserve
d
Reserve
d
wwwwwww
w
000000
00
0x07 Port 3 Interrupt
Enable
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
P3.1 Intr
Enable
P3.0 Intr
Enable
wwwwwww
w
000000
00
0x08 GPIO Configu-
ration
Port 3
Config
Bit 1
Port 3
Config
Bit 0
Port 2
Config
Bit 1
Port 2
Config
Bit 0
Port 1
Config
Bit 1
Port 1
Config
Bit 0
Port 0
Config
Bit 1
Port 0
Config
Bit 0
bbbbbbbb
000000
00
0x09 HAPI/I2C Configu-
ration
I2C
Position
Reserve
d
Reserve
d
Reserve
d
Reserve
d
Reserve
d
I2C Port
Width
Reserve
d
bbbbbbbb
000000
00
0x10 USB Device
Address A
Device
Address
A Enable
Device
Address
A
Bit 6
Device
Address
A
Bit 5
Device
Address
A
Bit 4
Device
Address
A
Bit 3
Device
Address
A
Bit 2
Device
Address
A
Bit 1
Device
Address
A
Bit 0
bbbbbbbb
000000
00
Notes:
5.
B: Read and Write.
6.
W: Write.
7.
R: Read.
Table 20-3. Details of Modes for Differing Traffic Conditions (see Table 20-2 for the decode legend) (continued)
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
