MT9174AE datasheet(3/22 Pages) MITEL

3 / 22 page

Preliminary Information

MT9173/74

9-139

F0o/RCK

Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns

wide negative pulse indicating the end of the active channel times of the device to

allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.

C4/TCK

Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock

input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin

provides the transmit bit rate clock to the system.

OSC2

Oscillator Output. CMOS Output.

OSC1

Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical

Characteristics for OSC1 input requirements.

Precan

Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the

precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’,

the LOUT to the precanceller path is enabled and functions normally. An internal

pulldown (50 k

Ω) is provided on this pin.

1,6,

18,

20,

No Connection. Leave open circuit

LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When

logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin.

TEST

Test Pin.

Connect to VSS.

LIN

Receive Signal input (Analog).

VDD

Positive Power Supply (+5V) input.

Pin Description (continued)

Pin #

Name

Description

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