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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MT9174AE датащи(PDF) 17 Page - Mitel Networks Corporation |
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MT9174AE датащи(HTML) 17 Page - Mitel Networks Corporation |
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17 / 22 page  Preliminary Information MT9173/74 9-153 † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Duty cycle is measured at VDD/2 volts. . † Timing is over recommended temperature & power supply voltages. * Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing. Notes: 1) When operating as a SLAVE the C4 clock has a 40% duty cycle. 2) When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e., FC=2.5xfC4). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from 0 ns to tC4P . However, the relative jitter must be less than JC (see Figure 17). Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams AC Electrical Characteristics† - Voltages are with respect to ground (V SS) unless otherwise stated. Characteristics Sym Min Typ* Max Units Test Conditions 1 I N P U T S Input Voltage (LIN) VIN 5.0 Vpp 2 Input Impedance (LIN)ZIN 20 k Ω fBaud=160 kHz 3 Crystal/Clock Frequency fC 10.24 MHz 4 Crystal/Clock Tolerance TC -100 0 +100 ppm 5a Crystal/Clock Duty Cycle DCC 40 50 60 % Normal temp. & VDD 5b Crystal/Clock Duty Cycle DCC 45 50 55 % Recommended at max./ min. temp. & VDD 6 Crystal/Clock Loading CL 33 50 pF From OSC1 & OSC2 to VSS. 7 O U T P U T S Output Capacitance (LOUT)Co 8pF 8 Load Resistance (LOUT) (VBias, VRef) RLout 500 100 Ω k Ω 9 Load Capacitance (LOUT) (VBias, VRef) CLout 0.1 20 pF µF Capacitance to VBias. 10 Output Voltage (LOUT)Vo 3.2 4.3 4.6 Vpp RLout = 500Ω, CLout = 20pF AC Electrical Characteristics† - Clock Timing - DN Mode (Figures 16 & 17) Characteristics Sym Min Typ* Max Units Test Conditions 1 C4 Clock Period tC4P 244 ns 2 C4 Clock Width High or Low tC4W 122 ns In Master Mode - Note 1 3 Frame Pulse Setup Time tF0S 50 ns 4 Frame Pulse Hold Time tF0H 50 ns 5 Frame Pulse Width tF0W 244 ns 6 10.24 MHz Clock Jitter (wrt C4) JC ±15 ns Note 2 Channel 31 Bit 0 Channel 0 Bit 7 Channel 0 Bit 6 F0 C4 ST-BUS BIT CELLS |
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