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RT3607CE датащи(PDF) 3 Page - Richtek Technology Corporation

номер детали RT3607CE
подробное описание детали  Multi-Phase PWM Controller for CPU Core Power Supply
PDF  69 Pages
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производитель  RICHTEK [Richtek Technology Corporation]
домашняя страница  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT3607CE датащи(HTML) 3 Page - Richtek Technology Corporation

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RT3607CE
DS3607CE-01 June 2016
www.richtek.com
©
Copyright 2016 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Pin No
Pin Name
Pin Function
17
SET3
3rd Platform setting. Platform can use this pin to set VR address, Zero load-line,
Anti-overshoot function and behavior, AI gain, Disable DVID compensation,
Decrease GTU and SA ramp (only in maximum phase = 1-phase), high frequency
ramp, DVID slew rate, and PSYS function for CORE VR and AXG VR.
18
SETA1
1st Platform Setting. Platform can use this pin to set OCS, DVID threshold and
ICCMAX for AXG VR.
19
SETA2
2nd Platform Setting. Platform can use this pin to set RSET, QRTH, QR width and
DVID width for AXG VR.
20
IMON
CPU CORE Current Monitor Output. This pin outputs a voltage proportional to the
loading current.
21
VREF
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the output
voltage of IMON pin. Between this pin and GND must be placed a exact 0.47
F
decoupling capacitor and a 1
 resistor.
22
IMONA
CPU AXG Current Monitor Output. This pin outputs a voltage proportional to the
loading current.
23
VR_HOT
Thermal Monitor Output, this Pin is Active Low.
24
ALERT
SVID Alert. (Active low)
25
VDIO
VR and CPU Data Transmission Interface.
26
VCLK
Synchronous Clock from the CPU.
27
EN
VR Enable Control Input.
29
VCC
Controller Power Supply. Connect this pin to 5V and place a decoupling capacitor
2.2
F at least. The decoupling capacitor is as close VR controller as possible.
31
IBIAS
Internal Bias Current Setting. Connect a 100k
 resistor from this pin tied to GND to
set the internal current. Don’t connect a bypass pass capacitor from this pin to GND.
32
RGNDA
Return Ground for AXG VR. This pin is the negative node of the differential remote
voltage sensing.
33
VSENA
AXG VR Voltage Sense Input. This pin is connected to the terminal of AXG VR
output voltage.
34
COMPA
AXG VR Compensation. This pin is error amplifier output pin.
35
FBA
Negative Input of the Error Amplifier. This pin is for AXG VR output voltage feedback
to controller.
36, 39, 40
ISENA[1:3]N Negative Current Sense Inputs of Multi-Phase AXG VR Channel 1, 2 and 3.
37, 38, 41
ISENA[1:3]P Positive Current Sense Inputs of Multi-Phase AXG VR Channel 1, 2 and 3.
42
TSENA
Thermal Sense Input for AXG VR.
43
TONSETA
AXG VR On-time Setting. A on-time setting resistor is connected from this pin to
input voltage.
45
DVD
Divided Input Voltage Detection of Power Stage. Connect this pin to a voltage
divider from input voltage of power stage to detect input voltage.
46, 47, 48
PWMA[1:3]
PWM Outputs for AXG VR of Channel 1, 2 and 3.
49
PS4
External Driver Enable Control. Connecting to driver enable pin. As received PS4
command, this pin will be low state.
50, 51, 52, 53 PWM[1:4]
PWM Outputs for CORE VR of Channel 1, 2, 3 and 4.
54
PGOOD
VR Ready Indicator.
55
TONSET
CORE VR On-time Setting. A on-time setting resistor is connected from this pin to
input voltage.
57
(Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to GND
for maximum power dissipation.



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