RT3607CE datasheet(49/69 Pages) RICHTEK

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RT3607CE

DS3607CE-01 June 2016

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Design Step :

RT3607CE Excel based design tool is available. Users

can contact your Richtek representative to get the

spreadsheet. Three main design procedures for RT3607CE

design, first step is initial settings, second step is loop

design and the last step is protection settings. The

following design example is to explain the RT3607CE

design procedure :

VCORE Specification

Input Voltage

12V

No. of Phases

ICCMAX

110A

ICC-DY

80A

ICC-TDC

85A

Load Line

1.7m



Fast Slew Rate

10mV/

s

Max Switching

Frequency

400kHz

In IMVP8 VRTB Guideline, the output filter requirements

of VRTB specification for desktop platform are :

Output Inductor : 220nH/0.49m

Output Bulk Capacitor : 560

μF/2.5V/5mΩ(max) 4 to 5pcs

Output Ceramic Capacitor : 22

μF/0805 (14pcs max in-

cavity)

Output Ceramic Capacitor : 10

μF/0805 (5pcs max

periphery)

(1) Initial Settings :



RT3607CE initial voltage is 0.9V



IBIAS needs to connect a 100k

Ω resistor to ground.



A voltage divider for setting DVD can choose RDVD_U =

510k

Ω and RDVD_L = 125kΩ to set VDVD > 2V,

RT3607CE enabled.

(2) Loop Design :



On time setting : Using the specification, TON is

TON

DAC

4.73p 1.2

1.2) 173n











Current sensor adopts lossless RC filter to sense

current signal in DCR. For getting an expect load

transient waveform, RxCx time constant needs to

match Lx/DCRx per phase. Cx = 0.47

μF is set, then

The on time setting resistor RTON = 330k

R960

0.47 F DCR









IMON resistor network design : TL = 25

°C, TR = 50°C

and TH = 100

°C are decided, NTC thermistor =

100k

Ω@25°C, β = 4485 and ICCMAX = 110A.

According to the sub-section “Current Loop Design in

Details”, RIMON1 = 7.32k

Ω, RIMON2 = 14.619kΩ and

RIMON3 = 14.177k

Ω can be decided. The REQ (25°C) =

20.82k

Ω.



Load-line design : 1.7m

Ω droop is requirement,

because R

EQ(25°C) has decided, the voltage loop Av

gain is also can be decided by following equation :



1 DCR







Where DCR(25

°C) = 0.49mΩ, RCS = 680Ω and

REQ(25

°C) = 20.82kΩ. Hence, the AV = R2 / R1 = 2.87

can be obtained. R1 = 10k

Ω is usually decided, so R2

= 28.66k

Ω.



Typical compensator design can use the following

equations to design the C1 and C2 values

OUT

80pF

R1 π f

ESR

98pF









For Intel platform, in order to induce the band width to

enhance transient performance to meet Intel's criterion,

the compensator of Zero can be designed close to 1/

10 of switching frequency.



SET1 resistor network design : First the ICCMAX is

designed as 110A. Next, OCP threshold is designed

as 1.5 x ICCMAX. Last, DVID compensation parameters

need to be decided. The DVID_TH can be calculated

as following equation :

DVID_TH

OUT

dVID

= LL C



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