IRCC datasheet(65/79 Pages) SMSC

65 / 79 page

BUS INTERFACE I/O

The Bus Interface I/O block contains a 128-byte

FIFO, DMA/Interrupt logic, and multiplexers to

control access to the FIFO and the ISA Bus

(Figure 34).

The Databus Multiplexer provides exclusive ISA

Bus access to either the 16550A UART or the

IrCC SCE depending on the state of Block Mode

Controls in the configuration registers. Disabled

blocks are tristated from the ISA Bus.

FIFO MULTIPLEXER

SCE FIFO Access

The FIFO Multiplexer controls the configuration

of the SCE FIFO in the Bus Interface I/O Block.

This configuration can be inferred from the state

of the SCE Modes bits in Line Control Register

when

the

transmit/receive

modes

are

disabled, or the transmit mode is enabled, the

FIFO is configured for transmit; otherwise, the

FIFO is configured for receive.

The signal

Transmit in Figure 34, above, can be satisfied by

the inverse of the SCE Modes msb; e.g., nD7.

HOST FIFO Access

The Host always has read access to the FIFO,

regardless of the state of the SCE Modes bits, or

the Loopback bit. The Host has write access to

the FIFO when the Loopback bit is inactive and

the transmit/receive modes are disabled or the

Transmit mode is enabled.

128-BYTE SCE FIFO

FIFO Timing & Controls

The FIFO uses interleaved access timing to allow

simultaneous

FIFO

data

reads

and

data

FIFO

Multiplexer

128-byte

FIFO

Transmit

Loopback

SCE

Databus Multiplexer

16550AUART

ISABus

Loopback

Transmit

Function

FIFO In toSCE Rx

FIFO Out toHost Bus

FIFO In toHost Bus

FIFO Out toSCE Tx

FIFO In toSCE Rx

FIFO Out toSCE Tx

I/O& Interrupt

Control

FIGURE 34 - BUS INTERFACE I/O BLOCK

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