IRCC datasheet(32/79 Pages) SMSC

32 / 79 page

Bus Status Register (Address 6)

FIFO Indicators (read-only)

The FIFO Indicators reflect the current status of

the SCE FIFO.

FIFO Not Empty, bit 7

The FIFO Not Empty bit when set to one

indicates that there is data in the SCE FIFO.

FIFO Full, bit 6

The FIFO Full bit when set to one indicates that

there is no room for data in the SCE FIFO.

Time-Out, bit 5

The Time-Out bit is the IOCHRDY time-out error

bit. The Time-Out bit when set to one indicates

that an IOCHRDY time-out error has occurred.

Time-Out is reset by the IrCC System Reset (see

Interface Description) following a read of the Bus

Status register, and following a Master Reset

(see Master Block Control Register).

registers (Table 18). Typically, the controls in

SCE before message transactions can occur.

Table 18 - Register Block One

Address

Direction

Description

Default

R/W

SCE Configuration Register A

'02'hex

aux

block control

bits

half

duplx

tx po-

larity

rx po-

larity

R/W

SCE Configuration Register B

'00'hex

output mux

bits

loop-

back

lpbck

tx crc

wait

string

move

dma

burst

dma

enable

R/W

FIFO Threshold Register

'00'hex

SCE Configuration Register A (Address 0)

Auxiliary IR, bit 7

When the Auxiliary IR bit is one and the active

device is routed through the Output Multiplexer to

the IR Port or the COM Port, the transmit signal

also appears at the Auxiliary Port.

Block Control, bits 3 - 6

The Block Control bits select one of the eight

IrCC operational modes (Table 19). The three

low-order Block Control bits are equivalent to the

IR Mode bits in the chip-level configuration space

of earlier devices; e.g., the FDC37C93X IR

Option Register, Serial Port 2, Logical Device 5,

legacy devices to accommodate IR Mode

selection

through

either

the

chip-level

configuration registers or the IrCC Block Control

bits; i.e., the last write from either source

determines the current mode selection and is

visible in both registers.

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