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MASTER TRANSMITTER WRITING TO A SLAVE RECEIVER (DAC7571) IN STANDARD/FAST

POWER-ON RESET

POWER-DOWN MODES

DAC7571

SLAS374A – FEBRUARY 2003 – REVISED JANUARY 2004

MODES

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the SDA line low while SCL is still high indicting that serial data transfer has started. This is called a start

condition, and can only be asserted by the master. After the start conditioin, the master generates the serial

clock and puts out an address byte. While generating the bit stream, the master ensures the timing for valid data.

For each valid I

address byte consists of 7 address bits (1001 100, assuming A0=0) and a direction bit (R/W=0). After sending

the address byte, the master generates a ninth SCL pulse and monitors the state of the SDA line during the high

period of this ninth clock cycle.

The SDA line being pulled low by a receiver during the high period of this 9

acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC7571 successfully

matched the address which the master sent. Upon the receipt of this acknowledge, the master knows that the

communication link with a DAC7571 has been established and more data can be sent. The master continues by

sending a Control/MS-byte, which sets DAC7571 operation mode and specifies the first 4 MSBs of data. After

sending the Control/MS-byte, the master expects an acknowledge signal from the DAC7571. Upon the receipt of

the acknowledge, the master sends an LS-byte that represents the 8 least significant bits of DAC7571's 12-bit

conversion data. After receiving the LS-byte, the DAC7571 sends an acknowledge. At the falling edge of the

acknowledge signal, following the LS-byte, the DAC7571 performs a digital to analog conversion. For further

DAC updates, the master can keep repeating Control/MS-byte and LS-byte sequences expecting an

acknowledge after each byte. After the required number of digital to analog conversions is complete, the master

can break the communication link with the DAC7571 by pulling the SDA line from low to high while SCL line is

high. This is called a stop condition . A stop condition brings the bus back to idle (SDA and SCL both high). A

stop condition indicates that communication with the DAC7571 has ended. All devices on the bus, including the

DAC7571, waits for a new start condition followed by a mtaching address byte. DAC7571 stays in a programmed

state until the receipt of a stop condition.

Table 1. Write Sequence in Standard/Fast Modes

Transmitter

MSB

6

5

4

3

2

1

LSB

Comment

Master

Start

Write Addressing (LSB=0, R/W =

Master

1

0

0

1

1

0

A0

0

0)

DAC7571

DAC7571 Acknowledges

Master

0

0

PD1

PD0

D11

D10

D9

D8

Writing Control/MS-Byte

DAC7571

DAC7571 Acknowledges

Master

D7

D6

D5

D4

D3

D2

D1

D0

Writing LS-Byte

DAC7571

DAC7571 Acknowledges

Master

Done

(1)

Once DAC7571 is addressed, high-byte-low-byte sequences can repeat until a stop condition is received.

(2)

Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.

The DAC7571 contains a power-on reset circuit that controls the output voltage during power-up. On power-up,

the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid

write sequence is made to the DAC. This is useful in applications where it is important to know the state of the

DAC output while it is in the process of powering up.

The DAC7571 contains four separate modes of operation. These modes are programmable via two bits (PD1

and PD0). Table 2 shows how the state of these bits correspond to the mode of operation.

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