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OUTPUT AMPLIFIER

I

Start

Condition

SDA

Stop

Condition

SDA

SCL

S

P

SCL

Not Acknowledge

Acknowledge

1

2

8

9

Clock Pulse for

Acknowledgement

S

START

Condition

Data Output

by Transmitter

Data Output

by Receiver

SCL From

Master

DAC7571

SLAS374A – FEBRUARY 2003 – REVISED JANUARY 2004

THEORY OF OPERATION (continued)

The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range

capabilities of the output amplifier can be seen in the typical characteristics. The slew rate is 1V/µs with a

half-scale settling time of 8 µs with the output unloaded.

The DAC7571 uses an I

I

described in the I

Mode (3.4 Mbit/s). Ten-bit addressing and general call addres are not supported.

For simplicity, standard mode and fast mode are referred to as F/S-mode and high-speed mode is referred tg as

HS-mode.

The 2-wire I

•

The Master initiates data transfer by establishing a Start condition. The Start condition is defined when a

high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41. The byte following

the start condition is the address byte consisting of the 7-bit slave address followed by the W bit.

Figure 41. START and STOP Conditions

•

The addressed Slave responds by pulling the SDA pin low during the ninth clock pulse, termed the

Acknowledge bit (see Figure 42). At this stage all other devices on the bus remain idle while the selected

device waits for data to be written to its shift register.

•

Data is transmitted over the serial bus in sequences of nine clock cycles (8 data bits followed by an

acknowledge bit. The transitions on the SDA line must occur during the low period of SCL and remain stable

during the high period of SCL (see Figure 43).

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