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WM8224 датащи(PDF) 45 Page - Cirrus Logic

номер детали WM8224
подробное описание детали  60MSPS 3-Channel AFE with Multiple Device Operation
PDF  50 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8224 датащи(HTML) 45 Page - Cirrus Logic

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WM8224
Production Data
w
PD, Rev 4.2, September 2013
45
REGISTER
REGISTER
NAME
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
R9 (09h)
BLC Red
Target
7:0
TARGETR
[7:0]
00000000
Target Black-Level code for Red channel. Please see the
Target Codes Section for details.
R10 (0Ah)
BLC Green
Target
7:0
TARGETG
[7:0]
00000000
Target Black-Level code for Green channel. Please see
the Target Codes Section for details.
R11 (0Bh)
BLC Blue
Target
7:2
TARGETB
[7:0]
00000000
Target Black-Level code for Blue channel. Please see the
Target Codes Section for details.
R12 (0Ch)
BLC Control
1
1:0
TG_METHOD
[1:0]
00
Determines the start-of-line method to be used.
00 = TG_REG method
01 = Not a valid option
10 = OEB/TG shared pin method, +ve edge triggered
11 = OEB/TG shared pin method, -ve edge triggered
2
TG_REG
0
Register flag to indicate a start-of-line, this register is
automatically set to zero after it has been clocked by the
BLC.
3
FSCALE_
REL
0
Inverts the Black-level target codes so they are relative to
fullscale.
4
RESERVED
0
Set to zero
6:5
RESERVED
00
Set to zero
7
STATE_OUT
0
Outputs the 2-bit state of the BLC onto OP0 and OP1.
R13 (0Dh)
BLC Control
2
2:0
CADUR[2:0]
000
Controls the number of Coarse Adjust iterations to be
performed.
3
FA_EN
0
Enables the Fine Adjust operation
7:4
RESERVED
0000
Set to zero
R14 (0Eh)
BLC Control
3
0
FRAME_
START
0
Register to indicate that the next start-of-line indicator is
the first line in a frame. This register is automatically set
to zero at the end of the BLC operation on the first line.
1
SEQ_START
0
Register to indicate that the next start-of-line indicator is
the first line of the first frame in a frame-sequence. This
register is automatically set to zero at the end of the BLC
operation on the first line.
2
FRAME_SEQ
0
Indicates that the BLC is to be used in a sequence of
frames
3
FA_ACCUM
0
Makes the Fine Adjust calibration accumulate a result over
multiple lines.
4
FA_
EVERYLINE
0
0 = Fine Adjust only used on the 1
st line of a frame
1 = Fine Adjust used on every line of a frame
5
CA_
EVERYLINE
0
0 = Coarse Adjust only used on the 1
st line of a frame
1 = Coarse Adjust used on every line of a frame
7:6
BPIX_AVAIL
[9:8]
00
MSBs of the number of Black-pixels available over which
to perform the Coarse and/or Fine Adjust Calibration.
R15 (0Fh)
BLC Control
4
7:0
BPIX_AVAIL
[7:0]
00000000
LSBs of the number of Black-pixels available over which to
perform the Coarse and/or Fine Adjust Calibration.
R32 (20h)
Offset DAC
(Red)
7:0
DACR[7:0]
10000000
Red channel 8-bit offset DAC value (mV) =
250*(DACR[7:0]-127.5)/127.5
R33 (21h)
Offset DAC
(Green)
7:0
DACG[7:0]
10000000
Green channel 8-bit offset DAC value (mV) =
250*(DACG[7:0]-127.5)/127.5
R34 (22h)
Offset DAC
(Blue)
7:0
DACB[7:0]
10000000
Blue channel 8-bit offset DAC value (mV) =
250*(DACB[7:0]-127.5)/127.5
R35 (23h)
Offset DAC
(RGB)
7:0
DACRGB[7:0]
-
A write to this register location causes the red, green and
blue offset DAC registers to be overwritten by the new
value
R36 (24h)
PGA Gain
LSB
(Red)
0
PGAR[0]
0
This register bit forms the LSB of the red channel PGA
gain code. PGA gain is determined by combining this
register bit and the 8 MSBs contained in register address
28 hex.



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