WM8224 datasheet(29/50 Pages) CIRRUS

29 / 50 page

WM8224

Production Data

PD, Rev 4.2, September 2013

MODE

MINIMUM NO. OF MCLKS PER

COARSE ADJUST ITERATION

3-Channel

2-Channel

Mono

Table 4 Modes vs MCLKs for Coarse Iterations

The BLC design rounds the Coarse Adjust iteration duration up to a whole number of pixels (i.e. the

iteration duration will be a whole number of VSMP periods).

FINE ADJUST CALIBRATION DURATION

The Fine Adjust calibration duration is determined by the number of remaining black pixels after the

coarse adjust has taken place.

BLC TEST MODE

This mode allows the status of the BLC to be seen on the 2 LSBs of the output data pins OP[1:0].

This mode could be enabled during the setup stage of the device to ensure that the black level

calibration does not encroach on the active pixel data. Set the STATEOUT register to enable this

mode. Once the BLC register values have been determined this register should be disabled. Table 5

shows the description of the output data.

DATA ON OP[1:0]

DESCRIPTION

No BLC

Dummy Pixels

Coarse Adjust Calibration

Fine Adjust Calibration

Table 5 Test Mode Outputs

BLC WORKED EXAMPLE:

Below is an example of how to configure the WM8224 for Black Level Calibration.

Assumptions

MCLK frequency

= 40MHz

VSMP frequency

= 13.33MHz

Mode of operation

= 3 Channel Mode

Black pixels on sensor

= 50

Dummy pixels on sensor

= 20

The following stages set up the Black Level calibration although not all stages may be required

depending on the application:

Set up the Dummy Pixel Delay

Define the Coarse Adjust Calibration

Define the Fine Adjust Calibration

WM8224 датащи(PDF) 29 Page - Cirrus Logic

WM8224 датащи(HTML) 29 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

датащи скачать

ссылки URL