WM8224 datasheet(44/50 Pages) CIRRUS

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WM8224

Production Data

PD, Rev 4.2, September 2013

NAME

BIT

NAME(S)

DEFAULT

DESCRIPTION

When TWOCHAN=1:

00 = Red PGA disabled (G&B only)

01 = Green PGA disabled (R&B only)

10 = Blue PGA

disabled (R&G

only)

11 = Reserved

R4 (04h)

Software

Reset

7:0

00100100

Any write to Software Reset causes all register bits to be

reset. It is recommended that a software reset be

performed after a power-up before any other register

writes.

Reading from this register returns the last 2 digits of the

device part number.

R5 (05h)

Device ID

Revision

7:0

00000001

Reading from this register returns the revision number of

the device.

R6 (06h)

Setup

3:0

Reserved

0000

Must be set to 0000

7:4

OPDEL[3:0]

000

Output latency adjust (ACLKDIV=00).

0000 = Minimum latency (7 MCLK periods)

0001 = 8 MCLK periods

0010 = 9 MCLK periods

0011 = 10 MCLK periods

0100 = 11 MCLK periods

0101 = 12 MCLK periods

0110 = 13 MCLK periods

0111 = 14 MCLK periods

1000 = 15 MCLK periods

1001 to 1111 = Invalid settings

R7 (07h)

Setup

REDPD

When set powers down red S/H, PGA

GRNPD

When set powers down green S/H, PGA

BLUPD

When set powers down blue S/H, PGA

ADCPD

When set powers down ADC. Allows reduced power

consumption without powering down the references which

have a long time constant when switching on/off due to the

external decoupling capacitors.

VRLCDACPD

When set powers down 4-bit RLCDAC, setting the output

to a high impedance state and allowing an external

reference to be driven in on the VRLC/VBIAS pin.

ADCREFPD

When set disables VRT, VRB buffers to allow external

references to be used.

7:6

Reserved

Must be set to 00

R8 (08h)

Setup

RESET_NO

REG

When set reset the digital clocking without register reset.

4:1

Reserved

0000

Must be set to 0

RLCEN

Reset Level Clamp Enable. When set Reset Level

Clamping is enabled. The method of clamping is

determined by CLAMPCTRL.

CLAMPCTRL

0 = RLC switch is controlled directly from RSMP input pin:

RSMP = 0: switch is open

RMSP = 1: switch is closed

1 = RLC switch is controlled by logical combination of

RSMP and VSMP.

RSMP && VSMP = 0: switch is open

Switch is re-opened when:

VSMP=0 (non-CDS mode)

VSMP=0 and RSMP=0 (CDS mode)

FOL_EN

Enables internal input voltage buffers, to minimise code

drift if not pixel clamping, when using an ac coupling

capacitor in non-CDS mode (CDS=0).

Line clamping should be used when this bit is set.

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