WM9710

Production Data

w

PD Rev 4.0 December 2003

20

Synchronisation of all AC-link data transactions is signalled by the WM9710 controller. The

WM9710 drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a

synchronisation signal to construct audio frames.

SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BITCLK). BITCLK, fixed at

12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and

incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The

receiver of AC-link data, (WM9710 for outgoing data and AC’97 controller for incoming data),

samples each serial bit on the falling edges of BITCLK.

The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a

valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position

of slot 0 indicates that the corresponding time slot within the current audio frame has been

assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the

responsibility of the source of the data, (the WM9710 for the input stream, AC’97 controller for the

output stream), to stuff all bit positions with 0s during that slot’s active time.

SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame.

The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder

of the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power

savings, all clock, sync, and data signals can be halted. This requires that the WM9710 be

implemented as a static design to allow its Register contents to remain intact when entering a

power savings mode.

PLAY MASTER VOLUME REGISTERS (INDEX 02H, 04H AND 06H)

These registers manage the output signal volumes. Register 02h controls the stereo master

volume (both right and left channels), Register 04h controls the stereo headphone out, and

Register 06h controls the mono volume output. Each step corresponds to 1.5dB. The MSB of the

register is the mute bit. When this bit is set to 1 the level for that channel is set at -

ML4 to ML0 is for left channel level, MR4 to MR0 is for the right channel and MM4 to MM0 is for

the mono out channel.

Support for the MSB of the volume level is not provided by the WM9710. If the MSB is written to,

then the WM9710 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver

writes a 1xxxxx the WM9710 interprets that as x11111. It will also respond when read with x11111

rather than 1xxxxx, the value written to it. The driver can use this feature to detect if support for

the 6th bit is there or not.

The default value of both the mono and the stereo registers is 8000h (1000 0000 0000 0000),

which corresponds to 0dB gain with mute on.

MUTE

MX4...MX0

FUNCTION

0

0 0000

0dB attenuation

0

0 0001

1.5dB attenuation

0

1 1111

46.5dB attenuation

1

x xxxx

Table 5 Volume Register Function

The Headphone out has an additional 6dB boost, selectable by setting HPB in register 74h.

PC BEEP REGISTER (INDEX 0AH)

This controls the level for the PC-beep input. Each step corresponds to approximately 3dB of

attenuation. The MSB of the register is the mute bit. When this bit is set to 1 the level for that

channel is set at -

WM9710 defaults to the PC-beep path being muted, so an external speaker should be provided

within the PC to alert the user to power on self-test problems.