HT45F65 datasheet(24/231 Pages) HOLTEK

24 / 231 page

Rev. 1.60

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Rev. 1.60

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HT45F65/HT45F66/HT45F67

Glucose Meter 8-Bit Flash MCU

System Architecture

Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed

totheirinternalsystemarchitecture.Therangeofthedevicestakeadvantageoftheusualfeatures

foundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhanced

performance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingand

instructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,with

theexceptionofbranchorcallinstructions.An8-bitwideALUisusedinpracticallyallinstruction

setoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,

decrement,branchdecisions,etc.Theinternaldatapathissimplifiedbymovingdatathroughthe

AccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryand

canbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalong

withadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequired

toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.This

makesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications.

Clocking and Pipelining

Themainsystemclock,derivedfromeitheraHXT,LXT,HIRC,LIRCorERCoscillatoris

subdividedintofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounteris

incrementedatthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.The

remainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4

clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakes

placeinconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat

instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions

wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich

casetheinstructionwilltakeonemoreinstructioncycletoexecute.

Fe tc h In st . ( PC )

Ex ec ut e In st . (P C- 1)

Fe tc h In st . (P C+ 1)

Ex ec ut e In st . (P C)

Fe tc h In st . (P C+ 2)

Ex ec ut e In st . (P C+ 1)

PC +1

PC +2

f SY S

(S yst em C lo ck)

P has e Cl o ck T1

Pr ogr am C oun te r

P has e Cl o ck T2

P has e Cl o ck T3

P has e Cl o ck T4

Pi pe lin in g

System Clocking and Pipelining

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