EPC635 datasheet(82/97 Pages) EPC

82 / 97 page

8.7. Register description: EEPROM Page-0 (0x80 ~ 0xFF)

8.7.1. CLK_enables

CLK_enables

CGU register, SEG0.*: Clock enable

0x80

Bit No.

Bit name

all_clks_en

mod_clk_sel

reserved

mod_clk_en

dll_clk_en

Operation

Default

0x3F

CGU clock enable register:

all_clks_en:

Force all clock enables

0: disable

1: enable

mod_clk_sel:

Select modulator clock source

0: mod_clk, from CGU

1: ext_mod_clk, from MODCLK input pin

mod_clk_en:

Modulator clock

0: disable

1: enable

dll_clk_en:

DLL clock

0: disable

1: enable

Note:

sys_clk is always running. It cannot be disabled.

8.7.2. MOD_CLK_divider

MOD_CLK_divider

CGU register, SEG0.*: MOD clock divider

0x85

Bit No.

Bit name

reserved

mod_clk_div

Operation

Default

0x01

mod_clk_div:

Provides the clock to the LED / pixel-field modulator/demodulator circuits, respectively, by integer division of the

PLL clock.

Default = 1: fmod_clk = 80MHz / (mod_clk_div + 1) = 80MHz / 2 = 40MHz

8.7.3. ISOURCE_CLK_divider

ISOURCE_CLK_divider

CGU register, SEG0.*: ISOURCE clock divider

0x88

Bit No.

Bit name

isource_clk_div

Operation

Default

0x4F

isource_clk_div:

Used for ADC conversion speed-up. Refer to chapter 5.7.3, Table 14 and Table 15.

Characteristics subject to change without notice

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Datasheet_epc635-V1.02

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