EPC635 datasheet(47/97 Pages) EPC

47 / 97 page

DCLK

SHUTTER

XSYNC_SAT_CFG

HSYNC_A1

VSYNC_A0

DATA[7:0]

DMA 1

Frame B - DCS3

Frame B - DCS2

Frame B - DCS1

Frame B - DCS0

Frame B – Calc. Distance

Appl. frame buffer

256kByte SDRAM

D-

D+

Application CPU

Appl. program memory

512kByte FLASH, serial

Frame A - DCS3

Frame A - DCS2

Frame A - DCS1

Frame A - DCS0

Frame A – Calc. Distance

SDRAM IF

SDA

SCL

epc635

Application

- Calc. Distance (3D)

- Cal. black & white (2D)

- Ctrl. INTs & DMAs

- Ctrl. epc635 via I2C & GPIO

- Ctrl. USB link with PC

- House keeping

Int. frame buffer C

128 - 512kByte SRAM

ARM / DSP Core

128kByte SRAM, Prog.

Figure 45: Time-shared application frame buffer CPU architecture

The second example is a time-shared application frame buffer CPU architecture. The epc635 must have a higher priority over CPU (see

Figure 45) when accessing the application frame buffer SDRAM. The memory is blocked to the CPU as long as epc635 is transferring the

burst. At the end of the burst, the memory channel is released by the DMA controller and the CPU gets access granted. In the time-shared

bus architecture, the application developer must carefully tune the bus access ratio between the epc635 and the CPU. This can be adjus-

ted by setting a different TCMI DCLK frequency (5, 10 or 20MHz) on the epc635 side. The higher the TCMI bus frequency, the faster the

burst is transmitted (min. burst duration for full pixel rows: 8µs at fDCLK= 20MHz).

Another option is using a CPU having a much wider and faster SDRAM interface. Example:

Assume using a CPU which has a 128 bit wide SDRAM bus running at 160MHz clock. The TCMI DCLK is set at 10MHz. This gives 4x per-

formance increase between FIFO → application SDRAM due to the TCMI to SDRAM bus clock ratio. Another 8x increase is due to 16-bit

packed samples in the FIFO and transferred over a 128 bit wide bus to the SDRAM. It results in a total of 32x faster transfers between

FIFO → application SDRAM, application SDRAM → internal SRAM of the CPU and vice-versa. This gives a lot of bandwidth to the CPU to

transfer data back and forth between the application SDRAM and the internal SRAM between computations.

Characteristics subject to change without notice

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Datasheet_epc635-V1.02

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