DS26401 datasheet(4/309 Pages) DALLAS

4 / 309 page

DS26401 Octal T1/E1/J1 Framer

11.13

E1 TRANSMIT CHANNEL BLOCKING REGISTERS .......................................................................................234

11.14

E1 TRANSMIT ELASTIC STORES OPERATION ............................................................................................235

ELASTIC STORE DELAY AFTER INITIALIZATION ........................................................................................................236

11.15

FRACTIONAL E1 SUPPORT (GAPPED CLOCK MODE).................................................................................239

11.16

ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 MODE) ....................................................240

11.17

TRANSMIT HDLC CONTROLLER...............................................................................................................247

11.18

HDLC TRANSMIT EXAMPLE.....................................................................................................................255

11.19

INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................256

11.20

INTERFACING THE E1 TRANSMITTER TO THE BERT ..................................................................................258

11.21

E1 TRANSMIT SYNCHRONIZER.................................................................................................................260

12.

BERT........................................................................................................................................262

12.1

BERT REGISTERS..................................................................................................................................262

12.2

BERT DESCRIPTION AND OPERATION .....................................................................................................263

12.3

PATTERN GENERATION ...........................................................................................................................264

12.4

PATTERN SYNCHRONIZATION...................................................................................................................265

12.5

BER CALCULATION.................................................................................................................................265

12.6

ERROR GENERATION ..............................................................................................................................265

12.7

BERT CONTROL REGISTERS ..................................................................................................................267

12.8

BERT STATUS REGISTER .......................................................................................................................271

12.9

PSEUDORANDOM PATTERN REGISTERS ...................................................................................................272

12.10

COUNT REGISTERS .................................................................................................................................274

12.11

RAM ACCESS.........................................................................................................................................275

13.

FUNCTIONAL TIMING .............................................................................................................276

13.1

DELAYS ..................................................................................................................................................276

13.2

T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................................277

13.3

T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................................282

13.4

E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS .........................................................................................286

13.5

E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS ...................................................................................288

14.

OPERATING PARAMETERS ...................................................................................................291

15.

TIMING.....................................................................................................................................292

15.1

MICROPROCESSOR BUS AC CHARACTERISTICS .......................................................................................292

15.2

RECEIVER AC CHARACTERISTICS............................................................................................................295

15.3

TRANSMIT AC CHARACTERISTICS............................................................................................................298

15.4

JTAG INTERFACE TIMING .......................................................................................................................301

15.5

SYSTEM CLOCK AC CHARACTERISTICS ...................................................................................................301

16.

JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...............................302

16.1

TAP CONTROLLER STATE MACHINE ........................................................................................................303

16.2

INSTRUCTION REGISTER..........................................................................................................................306

16.3

TEST REGISTERS....................................................................................................................................307

17.

PACKAGE INFORMATION ......................................................................................................308

18.

THERMAL INFORMATION ......................................................................................................309

19.

REVISION HISTORY................................................................................................................309

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