DS26401 datasheet(2/309 Pages) DALLAS

2 / 309 page

DS26401 Octal T1/E1/J1 Framer

TABLE OF CONTENTS

APPLICABLE STANDARDS ........................................................................................................7

FEATURES ..................................................................................................................................8

2.1

FRAMER/FORMATTER .....................................................................................................................................8

2.2

SYSTEM INTERFACE........................................................................................................................................8

2.3

HDLC CONTROLLERS ....................................................................................................................................9

2.4

TEST AND DIAGNOSTICS .................................................................................................................................9

2.5

CONTROL PORT..............................................................................................................................................9

BLOCK DIAGRAMS...................................................................................................................10

SIGNAL LIST (SORTED BY SIGNAL NAME) ............................................................................13

SIGNAL DESCRIPTIONS...........................................................................................................17

5.1

RECEIVE FRAMER SIGNALS...........................................................................................................................17

5.2

TRANSMIT FRAMER SIGNALS.........................................................................................................................19

5.3

PARALLEL CONTROL PORT............................................................................................................................20

5.4

SYSTEM INTERFACE......................................................................................................................................21

5.5

TEST............................................................................................................................................................22

REGISTER MAP.........................................................................................................................23

GLOBAL FUNCTIONS...............................................................................................................24

7.1

GLOBAL REGISTERS .....................................................................................................................................24

7.2

GLOBAL REGISTER DESCRIPTION AND OPERATION ........................................................................................25

7.3

IBO MULTIPLEXER........................................................................................................................................27

7.4

INTERRUPT TREE..........................................................................................................................................37

T1 RECEIVER ............................................................................................................................38

8.1

T1 RECEIVER REGISTER MAP .......................................................................................................................38

8.2

T1 RECEIVE FRAMER DESCRIPTION AND OPERATION.....................................................................................43

8.3

RECEIVE MASTER-MODE REGISTER..............................................................................................................44

8.4

INTERRUPT INFORMATION REGISTER .............................................................................................................44

8.5

T1 RECEIVE CONTROL REGISTERS ...............................................................................................................45

8.6

H.100 (CT BUS) COMPATIBILITY...................................................................................................................50

8.7

T1 RECEIVE STATUS AND INFORMATION........................................................................................................52

8.8

T1 RECEIVE-SIDE DIGITAL MILLIWATT CODE GENERATION ............................................................................63

8.9

T1 ERROR COUNT REGISTERS......................................................................................................................64

8.10

DS0 MONITORING FUNCTION ....................................................................................................................69

8.11

T1 RECEIVE SIGNALING OPERATION..........................................................................................................70

8.12

T1 RECEIVE PER-CHANNEL IDLE CODE INSERTION ....................................................................................76

8.13

RECEIVE-CHANNEL BLOCKING OPERATION ................................................................................................77

8.14

RECEIVE ELASTIC STORES OPERATION .....................................................................................................78

8.15

FRACTIONAL T1 SUPPORT (GAPPED-CLOCK MODE)...................................................................................82

8.16

T1 BIT-ORIENTED CODE (BOC) CONTROLLER...........................................................................................83

8.17

RECEIVE SLC-96 OPERATION...................................................................................................................85

8.18

RECEIVE FDL ...........................................................................................................................................86

8.19

PROGRAMMABLE IN-BAND LOOP-CODE DETECTION ...................................................................................87

8.20

RECEIVE HDLC CONTROLLER...................................................................................................................92

8.21

INTERLEAVED PCM BUS OPERATION (IBO) .............................................................................................100

8.22

INTERFACING THE T1 RX FRAMER TO THE BERT .....................................................................................102

T1 TRANSMIT ..........................................................................................................................104

9.1

T1 TRANSMIT REGISTER MAP .....................................................................................................................104

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