DS26401 datasheet(21/309 Pages) DALLAS

21 / 309 page

DS26401 Octal T1/E1/J1 Framer

Signal Name:

BTS

Signal Description:

Bus Type Select

Signal Type:

Input

Set high to select Motorola bus timing, low to select Intel bus timing. This pin controls the function of the RD (DS),

and WR (R/W) pins. If BTS = 1, these pins assume the function listed in parentheses ().

5.4 System Interface

Signal Name:

REF_CLK

Signal Description:

Reference Clock

Signal Type:

Input

A continuous T1 (1.544MHz) or E1 (2.048MHz) clock used to create GCLK_OUT and BPCLK.

Signal Name:

GCLK_OUT

Signal Description:

Global Clock Output

Signal Type:

Output

This output clock is generated from the REF_CLK input and is a 45MHz clock. This pin is usually connected to

GCLK_IN.

Signal Name:

GCLK_IN

Signal Description:

Global Clock Input

Signal Type:

Input

Primary clock for internal state machines. Can be connected to GCLK_OUT, or provided by the user. The GCLK_IN

frequency must be between 43MHz and 49MHz for proper operation.

Signal Name:

BPCLK

Signal Description:

Backplane Clock

Signal Type:

Output

Programmable clock output created from REFCLK. Can be set to 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz.

Signal Name:

RESET

Signal Description:

System Reset

Signal Type:

Input

Active-low reset. Forcing this input low sets all internal registers to their default value.

Signal Name:

HIZE

Signal Description:

High-Z Enable

Signal Type:

Input

Active high. Forcing this input high when the RESET and JTRST pins are low will hold all outputs in high-impedance

mode.

DS26401 датащи(PDF) 21 Page - Dallas Semiconductor

DS26401 датащи(HTML) 21 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL