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AD8331 датащи(PDF) 26 Page - Analog Devices |
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AD8331 датащи(HTML) 26 Page - Analog Devices |
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26 / 32 page ![]() AD8331/AD8332 Rev. C | Page 26 of 32 15 16 20 17 18 19 8 7 6 5 1 4 3 2 9 13 10 COMM VIP LOP COML LMD LON VPS INH COMM ENBV ENBL GAIN 0.1 µF HILO +5V +5V CFB 0.018 µF NC VOH VOL VOUT VPOS +5V 14 11 12 VCM RCLMP NC NC NC VIN 0.1 µF AD8331 MODE GAIN MODE VCM CLMP HILO VIN Figure 74. Disabling the LNA INH LNA 5 Ω LMD LOP ADG736 LON 200 Ω 50 Ω 0.1 µF 18nF SELECT RFB 280 Ω 1.13k Ω AD8332 5 Ω Figure 75. Accommodating Multiple Sources MEASUREMENT CONSIDERATIONS Figure 51 through Figure 55 show typical measurement configurations and proper interface values for measurements with 50 Ω conditions. Short-circuit input noise measurements are made using Figure 53. The input-referred noise level is determined by dividing the output noise by the numerical gain between Point A and Point B and accounting for the noise floor of the spectrum analyzer. The gain should be measured at each frequency of interest and with low signal levels since a 50 Ω load is driven directly. The generator is removed when noise measurements are made. ULTRASOUND TGC APPLICATION The AD8332 ideally meets the requirements of medical and industrial ultrasound applications. The TGC amplifier is a key subsystem in such applications, since it provides the means for echolocation of reflected ultrasound energy. Figure 76 through Figure 78 are schematics of a dual, fully differential system using the AD8332 and AD9238 12-bit high speed ADC with conversion speeds as high as 65 MSPS. In this example, the VGA outputs are dc-coupled, using the reference output of the ADC and a level shifter to center the common- mode output voltage to match that of the converter. Consult the data sheet of the converter to determine whether external CMV biasing is required. AC coupling is recommended if the CMV of the VGA and ADC are widely disparate. Using the circuit shown, and a high speed ADC FIFO evaluation kit connected to a laptop PC, an FFT can be performed on the AD8332. With the on-board clock of 20 MHz, and minimal low-pass filtering, and both channels driven with a 1 MHz filtered sine wave, the THD is –75 dB, noise floor –93 dB and HD2 –83 dB. |
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