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AD8331 датащи(PDF) 24 Page - Analog Devices |
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AD8331 датащи(HTML) 24 Page - Analog Devices |
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24 / 32 page ![]() AD8331/AD8332 Rev. C | Page 24 of 32 Table 4. Clamp Resistor Values Clamp Resistor Value (kΩ) Clamp Level (V p-p) HILO = LO HILO = HI 0.5 1.21 1.0 2.74 2.21 1.5 4.75 4.02 2.0 7.5 6.49 2.5 11 9.53 3.0 16.9 14.7 3.5 26.7 23.2 4.0 49.9 39.2 4.4 100 73.2 Output Filtering and Series Resistor Requirements To ensure stability at the high end of the gain control range, series resistors or ferrite beads are recommended for the outputs when driving large capacitive loads, or circuits on other boards,. These components can be part of the external noise filter. Recommended resistor values are 84.5 Ω for LO gain mode and 100 Ω for HI gain mode (see Figure 66) and are placed near Pins VOH and VOL. Lower value resistors are permissible for applications with nearby loads or with gains less than 40 dB. Lower values are best selected empirically. An antialiasing noise filter is typically used with an ADC. Filter requirements are application dependent. When the ADC resides on a separate board, the majority of filter components should be placed nearby to suppress noise picked up between boards and mitigates charge kickback from the ADC inputs. Any series resistance beyond that required for output stability should be placed on the ADC board. Figure 70 shows a second order low-pass filter with a bandwidth of 20 MHz. The capacitor is chosen in conjunction with the 10 pF input capacitance of the ADC. 18pF OPTIONAL BACKPLANE 84.5 Ω 0.1 µF 0.1 µF 1.5 µH 1.5 µH 158 Ω 158 Ω 84.5 Ω ADC Figure 70. 20 MHz Second-Order Low-Pass Filter DRIVING ADCS The output drive will accommodate a wide range of ADCs. The noise floor requirements of the VGA will depend on a number of application factors, including bit resolution, sampling rate, full-scale voltage, and the bandwidth of the noise/antialias filter. The output noise floor and gain range can be adjusted by selecting HI or LO gain mode. The relative noise and distortion performance of the two gain modes can be compared in Figure 21 and Figure 27 through Figure 37. The 48 nV/√Hz noise floor of the LO gain mode is suited to converters with higher sampling rates or resolutions (such as 12 bits). Both gain modes can accommodate ADC full- scale voltages as high as 4 V p-p. Since distortion performance remains favorable for output voltages as high as 4 V p-p (see Figure 32), it is possible to lower the output-referred noise even further by using a resistive attenuator (or transformer) at the output. The circuit in Figure 71 has an output full-scale range of 2 V p-p, a gain range of –10.5 dB to +37.5 dB, and an output noise floor of 24 nV/√Hz, making it suitable for some 14-bit ADC applications. VOH VOL LPF 4V p-p DIFF, 48n V/ 187 Ω 2V p-p DIFF, 24n V/ 2:1 374 Ω HZ 187 Ω ADC AD6644 HZ Figure 71. Adjusting the Noise Floor for 14-Bit ADCs OVERLOAD These devices respond gracefully to large signals that overload its input stage and to normal signals that overload the VGA when the gain is set unexpectedly high. Each stage is designed for clean-limited overload waveforms and fast recovery when gain setting or input amplitude is reduced. Signals larger than ±275 mV at the LNA input are clipped to 5 V p-p differential prior to the input of the VGA. Figure 44 shows the response to a 1 V p-p input burst. The symmetric overload waveform is important for applications, such as CW Doppler ultrasound, where the spectrum of the LNA outputs during overload is critical. The input stage is also designed to accommodate signals as high as ±2.5 V without triggering the slow-settling ESD input protection diodes. Both stages of the VGA are susceptible to overload. Postamp limiting is more common and results in the clean-limited output characteristics found in Figure 45. Under more extreme conditions, the X-AMP will overload, causing the minor glitches evident in Figure 46. Recovery is fast in all cases. The graph in Figure 72 summarizes the combinations of input signal and gain that lead to the different types of overload. |
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