AD8331 datasheet(23/32 Pages) AD

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AD8331/AD8332

Rev. C | Page 23 of 32

Gain Input

Pin GAIN is common to both channels of the AD8332. The

input impedance is nominally 10 MΩ and a bypass capacitor

from 100 pF to1 nF is recommended.

Parallel connected devices may be driven by a common voltage

source or DAC. Decoupling should take into account any

bandwidth considerations of the drive waveform, using the total

distributed capacitance.

If gain control noise in LO gain mode becomes a factor,

maintaining ≤15 nV/√Hz noise at the GAIN pin will ensure

satisfactory noise performance. Internal noise prevails below

15 nV/√Hz at the GAIN pin. Gain control noise is negligible in

HI gain mode.

VCM Input

The common-mode voltage of Pins VCM, VOL, and VOH

defaults to 2.5 Vdc. With output ac-coupled applications, the

VCM pin will be unterminated; however, it must still be

bypassed in close proximity for ac grounding of internal

circuitry. The VGA outputs may be dc connected to a

differential load, such as an ADC. Common-mode output

voltage levels between 1.5 V and 3.5 V may be realized at Pins

VOH and VOL by applying the desired voltage at Pin VCM.

DC-coupled operation is not recommended when driving loads

on a separate PC board.

The voltage on the VCM pin is sourced by an internal buffer

with an output impedance of 30 Ω and a ±2 mA default output

current (see Figure 68). If the VCM pin is driven from an

external source, its output impedance should be <<30 Ω and its

current drive capability should be >>2 mA. If the VCM pins of

several devices are connected in parallel, the external buffer

should be capable of overcoming their collective output

currents. When a common-mode voltage other than 2.5 V is

used, a voltage-limiting resistor, RCLMP, is needed to protect

against overload.

VCM

NEW VCM

RO << 30Ω

100pF

2mA MAX

Ω

0.1

µF

INTERNAL

CIRCUITRY

AC GROUNDING FOR

INTERNAL CIRCUITRY

Figure 68. VCM Interface

Logic Inputs—ENB, MODE, and HILO

The input impedance of all enable pins is nominally 25 kΩ and

may be pulled up to 5 V (a pull-up resistor is recommended) or

driven by any 3 V or 5 V logic families. The enable pins perform

a power-down function, when disabled, the VGA outputs are

near ground. Multiple devices may be driven from a common

source. Consult the pin-function tables for circuit functions

controlled by the enable pins.

Pin HILO is compatible with 3 V or 5 V CMOS logic families. It

is either connected to ground or pulled up to 5 V, depending on

the desired gain range and output noise.

Optional Output Voltage Limiting

The RCLMP pin provides the user with a means to limit the

output voltage swing when used with loads that have no

provisions for prevention of input overdrive. The peak-to-peak

limited voltage is adjusted by a resistor to ground, and Table

lists several voltage levels and the corresponding resistor value.

Unconnected, the default limiting level is 4.5 V p-p.

Note that third harmonic distortion will increase as waveform

amplitudes approach clipping. For lowest distortion, the clamp

level should be set higher than the converter input span. A

clamp level of 1.5 V p-p is recommended for a 1 V p-p linear

output range, 2.7 V p-p for a 2 V p-p range, or 1 V p-p for a

0.5 V p-p operation. The best solution will be determined

experimentally. Figure 69 shows third harmonic distortion

as a function of the limiting level for a 2 V p-p output signal.

A wider limiting level is desirable in HI gain mode.

5.0

–50

–40

–30

–80

–70

–60

2.0

3.5

1.5

3.0

2.5

4.0

4.5

–20

CLAMP LIMIT LEVEL (V p-p)

VGAIN = 0.75V

HILO = HI

HILO = LO

Figure 69. HD3 vs. Clamping Level for 2 V p-p Differential Input

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