Electrical specifications

STA333SML

10/17

DocID025317 Rev 2

3.6

Power-off sequence

The power-off sequence shown in Figure 3 below ensures a pop-free turn-off.

Figure 3. Power-off sequence

3.7

Testing

Figure 4. Test circuit

Figure 5. Current deadtime test circuit

Don’t care

Don’t care

Don’t care

Don’t care

Don’t care

Don’t care

No specific VCC and VDD_DIG turn-off sequence is required

VCC

VDD_DIG

XTI

Low current dead time = MAX(DTr,DTf)

OUTxY

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

t

DTf

DTr

Duty cycle = 50%

INxY

OUTxY

gnd

+Vcc

M58

M57

R 8

Ω

+

-

V67 =

vdc = Vcc/2

D03AU1458

High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

Rload=8

Ω

Q2

OUTB

)

B

(

n

i

T

D

)

B

(

t

u

o

T

D

DTout(A)

C71 470nF

C70

470nF

C69

470nF

Iout=4A

Iout=4A

Q4

Q1

Q3

M64

INB

M63

D03AU1517

M58

INA

M57

DTin(A)

Duty cycle=A

Duty cycle=B

Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure

L68 22

μ

L67 22

μ

OUTA

Lout = 1.5 A

Lout = 1.5 A