Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance

state.

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

MARCH 2008

MARCH/2008, V 1.0

Alliance Memory Inc.

Page 7 of 12

AS6C4016

256K X 16 BIT SUPER LOW POWER CMOS SRAM