AC TEST CONDITIONS

Input Pulse Levels

Input Rise and Fall Times

3ns

Input and Output Timing Reference Levels

1.5V

Output Load

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

AS6C4016-55

PARAMETER

SYM.

MIN.

MAX.

UNIT

Read Cycle Time

55

-

ns

Address Access Time

-

55

ns

Chip Enable Access Time

-

55

ns

Output Enable Access Time

-

30

ns

Chip Enable to Output in Low-Z

10

-

ns

Output Enable to Output in Low-Z

5

-

ns

Chip Disable to Output in High-Z

-

20

ns

Output Disable to Output in High-Z

-

20

ns

Output Hold from Address Change

10

-

ns

LB#, UB# Access Time

-

55

ns

LB#, UB# to High-Z Output

-

25

ns

LB#, UB# to Low-Z Output

10

-

ns

(2) WRITE CYCLE

AS6C4016-55

PARAMETER

SYM.

MIN.

MAX.

UNIT

Write Cycle Time

55

-

ns

Address Valid to End of Write

50

-

ns

Chip Enable to End of Write

50

-

ns

Address Set-up Time

0

-

ns

Write Pulse Width

45

-

ns

Write Recovery Time

0

-

ns

Data to Write Time Overlap

25

-

ns

Data Hold from End of Write Time

0

-

ns

Output Active from End of Write

5

-

ns

Write to Output in High-Z

-

20

ns

LB#, UB# Valid to End of Write

45

-

ns

*These parameters are guaranteed by device characterization, but not production tested.

512K X 8 BIT LOW POWER CMOS SRAM

January 2007

MARCH 2008

MARCH/2008, V 1.0

Alliance Memory Inc.

Page 4 of 12

AS6C4016

256K X 16 BIT SUPER LOW POWER CMOS SRAM