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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TP3094 датащи(PDF) 16 Page - National Semiconductor (TI) |
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TP3094 датащи(HTML) 16 Page - National Semiconductor (TI) |
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16 / 19 page  16 www.national.com Timing Specifications Clock and Data Timing All timing parameters are measured at VOH=2.0V and VOL=0.7V Long Frame Timing Note: when measuring signals going to TRI-STATE®, the timing delay is measured when the signal is 10% away from the starting level. Symbol Parameter Conditions Min Typ Max Units 1/tPM Frequency of MCLK 1.536 1.544 2.048 4.096 8.192 MHz MHz MHz MHz MHz DCMCLK MCLK Duty Cycle 40 60 % tRM Rise time of MCLK 10 ns tFM Fall time of MCLK 10 ns tSDB Setup time DR valid to MCLK low 20 ns tHDB Hold time DR valid from MCLK low 20 ns tDBD Delay from MCLK high to DX valid CL=100pF+2LSTTL loads 0 35 ns tDZC Delay from MCLK high to DX disabled CL=100pF+2LSTTL loads 20 ns tTSZC Delay from MCLK high to TSX disabled CL=100pF+2LSTTL loads 20 ns tDBTS Delay time to TSX low CL = 0pF to 150pF 50 ns tPDN PDN persistence 16xtPM tSF Set-up Time from FS to MCLK Low Short Frame Sync Pulse 20 ns tHF Hold Time from MCLK Low to FS Low Short Frame Sync Pulse 20 ns Symbol Parameter Conditions Min Typ Max Units tHBFL Holding time from Clock to Frame Sync Long Frame Only 10 ns tSBF Set-up time from Frame Sync to Clock low Long Frame Only 35 ns tZDF Delay time Valid Data from FS or MCLK, whichever comes later CL = 0pF to 150pF 50 ns |
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