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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F101XF датащи(PDF) 99 Page - STMicroelectronics |
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STM32F101XF датащи(HTML) 99 Page - STMicroelectronics |
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99 / 117 page  DocID16553 Rev 5 99/117 STM32F101xF, STM32F101xG Electrical characteristics Figure 51. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. tSETTLING Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB -3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5kΩ Update rate(1) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) -- 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5kΩ tWAKEUP(1) Wakeup time from off state (Setting the ENx bit in the DAC Control register) -6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5kΩ input code between lowest and highest possible ones. PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. Preliminary values. 2. Guaranteed by design. 3. Quiescent mode refers to the state of the DAC when a steady value is kept on the output so that no dynamic consumption is involved. Table 60. DAC characteristics (continued) Symbol Parameter Conditions Min Typ Max(1) Unit Comments |
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