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STM32F101XF датащи(PDF) 90 Page - STMicroelectronics

номер детали STM32F101XF
подробное описание детали  Single-cycle multiplication and hardware division
PDF  117 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101XF датащи(HTML) 90 Page - STMicroelectronics

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Electrical characteristics
STM32F101xF, STM32F101xG
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DocID16553 Rev 5
Table 55. SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
-
18
MHz
Slave mode
-
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)(1)
NSS setup time
Slave mode
4tPCLK
-
ns
th(NSS)(1)
NSS hold time
Slave mode
2tPCLK
-
tw(SCKH)(1)
tw(SCKL)(1)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
Master mode
5
-
Slave mode
5
-
th(MI) (1)
Data input hold time
Master mode
5
-
th(SI)(1)
Slave mode
4
-
ta(SO)(1)(2)
Data output access time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tdis(SO)(1)(3) Data output disable time Slave mode
2
10
tv(SO) (1)(1)
Data output valid time
Slave mode (after enable edge)
-
25
tv(MO)(1)(1)
Data output valid time
Master mode (after enable edge)
-
5
th(SO)(1)
Data output hold time
Slave mode (after enable edge)
15
-
th(MO)(1)
Master mode (after enable edge)
2
-
1. Guaranteed by characterization results.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z



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