ST72321R7-Auto datasheet(43/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

Supply, reset and clock management

Doc ID 13829 Rev 1

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6.6

System integrity management (SI)

The System Integrity Management block contains the Low Voltage Detector (LVD) and

Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.

6.6.1

Low voltage detector (LVD)

The low voltage detector function (LVD) generates a static reset when the VDD supply

voltage is below a VIT- reference value. This means that it secures the power-up as well as

the power-down keeping the ST7 in reset.

The VIT- reference value for a voltage drop is lower than the VIT+ reference value for power-

on in order to avoid a parasitic reset when the MCU starts running and sinks current on the

supply (hysteresis).

The LVD reset circuitry generates a reset when VDD is below:

–VIT+ when VDD is rising

–VIT- when VDD is falling

The LVD function is illustrated in Figure 14.

The voltage threshold can be configured by option byte to be low, medium or high.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-, the

MCU can only be in two modes:

–

under full software control

–

in static safe reset

In these conditions, secure operation is always ensured for the application without the need

for external reset hardware.

During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to

reset other devices.

Note:

The LVD allows the device to be used without any external RESET circuitry.

If the medium or low thresholds are selected, the detection may occur outside the specified

operating voltage range. Below 3.8V, device operation is not guaranteed.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from Reset, to ensure the application functions properly.

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