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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72321R7-Auto датащи(PDF) 42 Page - STMicroelectronics |
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ST72321R7-Auto датащи(HTML) 42 Page - STMicroelectronics |
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42 / 243 page  Supply, reset and clock management ST72321xx-Auto 42/243 Doc ID 13829 Rev 1 6.5.5 Internal watchdog RESET The RESET sequence generated by an internal Watchdog counter overflow is shown in Figure 13. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 13. RESET sequences VDD RUN RESET PIN EXTERNAL WATCHDOG Active Phase VIT+(LVD) VIT-(LVD) th(RSTL)in tw(RSTL)out RUN th(RSTL)in Active WATCHDOG UNDERFLOW tw(RSTL)out RUN RUN RUN RESET RESET SOURCE SHORT EXT. RESET LVD RESET LONG EXT. RESET WATCHDOG RESET INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH tw(RSTL)out Phase Active Phase Active Phase DELAY |
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