ST10F296 datasheet(245/346 Pages) STMICROELECTRONICS

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ST10F296E

Power reduction modes

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The ST10F296E core module, which generates the RAM control signals, is powered by the

internal V18 supply. During turning off transient phase these control signals follow the V18,

while RAM is switched to V18SB internal reference. A high level of RAM write strobe from the

ST10F296E core (active low signal), may be low enough to be recognized as a logic 0 by

the RAM interface (due to V18 being lower than V18SB). The bus status may contain a valid

address for the RAM and an unwanted data corruption may occur. For this reason, an extra

interface, powered by the switched supply, is used to prevent the RAM from such potential

corruption mechanisms.

Warning:

During power-off phase, the external hardware must maintain

a stable ground level on the RSTIN pin, with no glitches, to

avoid spurious exits from reset status due to an unstable

power supply.

21.3.2

Exiting standby mode

The procedure to exit standby mode consists of a standard power-on sequence where the

RAM is powered through the V18SB internal reference (derived from the VSTBY pin external

voltage).

It is recommended to hold the device under reset (RSTIN pin forced low) until the external

VDD voltage pin is stable. At the beginning of the power-on phase, the device is maintained

under reset by the internal low voltage detector circuit (implemented inside the main voltage

regulator) until the internal V18 becomes higher than about 1.0 V. Despite this, there is no

warranty that the device stays under reset status if RSTIN is at high level during

power ramp up.

It is imperative that the external hardware guarantees a stable ground level on the

RSTIN pin along the power-on phase, without any temporary glitches.

The external hardware is responsible for driving the RSTIN pin low until the VDD is stable,

even though the internal LVD is active. An additional time period of at least 1 ms is also

requested to allow the internal voltage regulator to stabilize before releasing the RSTIN pin.

This is necessary because the internal Flash has to begin its initialization phase (which

starts when the RSTIN pin is released) with a stable V18.

Once the internal reset signal goes low, the power supply of the RAM (which is still frozen) is

switched to the main V18.

At this point, all voltages are stable, and the execution of the initialization routines can start.

The XRAM2EN bit can be set and the RAM can be enabled.

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