ST10F296 datasheet(222/346 Pages) STMICROELECTRONICS

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System reset

ST10F296E

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20.3.2

Exit from synchronous reset state

The reset sequence is extended until the RSTIN level becomes high. It is also internally

prolonged by the Flash initialization when EA = 1 (internal memory selected). Then, the

code execution restarts. The system configuration is latched from Port 0, and the ALE, RD

and WR/WRL pins are driven to their inactive level. The device starts program execution

from memory location 00'0000h in code segment 0. This starting location typically points to

the general initialization routine.

Figure 79 and Figure 80 show the timing of synchronous reset sequences when booting

from internal or external memory respectively. They emphasize a short reset event

degenerating into a long reset.

Figure 81 and Figure 82 shows the timing of a typical synchronous long reset when booting

from internal or external memory respectively.

20.3.3

Synchronous reset and the RPD pin

When the RSTIN pin is pulled low (by external hardware or as a consequence of a

bidirectional reset), the RPD internal weak pull-down is activated. The external capacitance

(if any) on the RPD pin is slowly discharged through the internal weak pull-down. If the

voltage level on the RPD pin reaches the input low threshold (c. 2.5 V), the reset event

becomes immediately asynchronous.If a short or long hardware reset occurs, the situation

illustrated in Figure 77 takes place.

If RPD rises above the input threshold, the asynchronous reset is completed. To complete a

synchronous reset normally, the capacitance must be big enough to maintain the voltage on

the RPD pin sufficiently high for the duration of the internal reset sequence.

For software or watchdog reset events, an active synchronous reset is completed regardless

of the RPD status.

The signal that makes that RPD status transparent under reset is the internal RSTF (after

the noise filter).

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