ST10F296 datasheet(221/346 Pages) STMICROELECTRONICS

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ST10F296E

System reset

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20.3.1

Short and long synchronous reset

Once the first 16 TCL elapse (4 TCL + 12 TCL), the internal reset sequence, of 1024 TCL

cycles, starts. When it is finished and when an additional 8 TCL have elapsed, the level of

the RSTIN pin is sampled (after the filter, see RSTF in Figure 75, Figure 76, Figure 77, and

Figure 78). If the RSTIN pin is high, a short reset is flagged (see Section 19: Watchdog

timer for details on reset flags). If the RSTIN pin is low, a long reset is flagged. The major

difference between long and short resets is that during a long reset, P0(15:13) also become

transparent, so it is possible to change the clock options.

Warning:

When there is a short pulse on the RSTIN pin, and when a

bidirectional reset is enabled, the RSTIN pin is held low by

the internal circuitry. At the end of 1024 TCL cycles, the

RTSIN pin is released, but due to the presence of the input

analog filter, the internal input reset signal (RSTF in

Figure 75, Figure 76, Figure 77, and Figure 78) is released

after it (50 to 500 ns after). This delay corresponds with the

additional 8 TCL. At the end of this delay, the internal input

reset line (RSTF) is sampled to elucidate if the reset event is

short or long.

Short or long reset events

●

If 8 TCL delay is > 500 ns (FCPU < 8 MHz), the reset event is always recognized as

short.

●

If 8 TCL delay is < 500 ns (FCPU > 8 MHz), the reset event could be recognized as

either short or long, depending on the real filter delay (between 50 and 500 ns) and the

CPU frequency. If RSTF samples high, a short reset is recognized. If RSTF samples

low, a long reset is recognized. Once the 8 TCL delay has elapsed with a long reset,

the P0(15:13) pins become transparent, and the system clock can be re-configured.

After the internal RSTF signal becomes high, Port 0 returns 3-4 TCL which are not

transparent.

The P0 pins become transparent and Port 0 returns 3-4 TCL which are not transparent

when a unidirectional reset is selected and when the RSTIN pin is held low untill the end of

an internal sequence (1024 TCL + max 16 TCL) and released at that time.

Note:

When the device runs with a CPU frequency lower than 40 MHz, the minimum valid reset

pulse recognized by the CPU (4 TCL) may be longer than the minimum analog filter delay

(50 ns). Consequently, a short reset pulse may not be filtered by the analog input filter.

However, this pulse is not long enough to trigger a CPU reset (as it is shorter than 4 TCL). It

generates a Flash reset, but, not a system reset. In this condition, the Flash always answers

with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.

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