ST10F296 datasheet(215/346 Pages) STMICROELECTRONICS

215 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296E

System reset

215/346

20.2

Asynchronous reset

An asynchronous reset is triggered when the RSTIN pin is pulled low while the RPD pin is at

low level. The ST10F296E device is immediately (after the input filter delay) forced into a

reset default state. It pulls the RSTOUT pin low, it cancels pending internal hold states (if

any), it aborts all internal/external bus cycles, it switches buses (data, address and control

signals) and I/O pin drivers to high-impedance, and it pulls the Port 0 pins high.

Note:

If an asynchronous reset occurs in the internal memories during a read or write phase, the

content of the memory itself could be corrupted. To avoid this, synchronous reset usage is

strongly recommended.

20.2.1

Power-on reset

The asynchronous reset must be used during the power-on of the device. Depending on the

crystal or resonator frequency, the on-chip oscillator needs about 1 ms to 10 ms to stabilize

(refer to Section 24: Electrical characteristics), with an already stable VDD. The logic of the

ST10F296E does not need a stabilized clock signal to detect an asynchronous reset, so it is

suitable for power-on conditions. To ensure a proper reset sequence, the RSTIN pin and the

RPD pin must be held low until the device clock signal is stabilized and the system

configuration value on Port 0 has settled.

At power-on, it is important to respect some additional constraints introduced by the start-up

phase of the different embedded modules.

In particular, the on-chip voltage regulator needs at least 1 ms to stabilize the internal 1.8 V

for the core logic. This time is computed from when the external reference (VDD) becomes

stable inside the specification range (that is at least 4.5 V). This is a constraint for the

application hardware (external voltage regulator). The RSTIN pin assertion must be

extended to guarantee the voltage regulator stabilization.

A second constraint is imposed by the embedded Flash. When booting from the internal

memory, starting from the RSTIN pin being released, the Flash needs a maximum of 1 ms

for its initialization. Before this, the internal reset (RST signal) is not released, so the CPU

does not start code execution in internal memory.

Note:

The above is not true if the external memory is used (pin EA held low during reset phase). In

this case, once the RSTIN pin is released, and after a few CPU clock (filter delay plus 3...8

TCL), the internal reset signal RST is released, afterwhich code execution can start

immediately. Eventual access to the data in the internal Flash is forbidden before its

initialization phase is complete. An eventual access during the starting phase returns FFFFh

at the beginning and 009Bh later on (an illegal opcode trap can be generated).

At power-on, the RSTIN pin must be tied low for a minimum period of time that includes the

start-up time of the main oscillator (tSTUP = 1 ms for the resonator, 10 ms for the crystal) and

the PLL synchronization time (tPSUP = 200 µs). Consequently, if the internal Flash is used,

the RSTIN pin could be released to recover some time in the start-up phase (Flash

initialization needs a stable V18, but, does not need a stable system clock since an internal

dedicated oscillator is used) before the main oscillator and PLL are stable.

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 датащи(PDF) 215 Page - STMicroelectronics

ST10F296 датащи(HTML) 215 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL